Yujeong Shim

Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed. The key ideas of the proposed modeling method are to decompose the chip-package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structures impedance by using a segmentation method. For the impedance calculations of the independently decomposed structures, a new method based on proposed analytic expressions is introduced for a chip level PDN, a resonant cavity model is used for a package level PDN, and equivalent circuit models are used for interconnections. The proposed method has been successfully verified by comparisons with measurements using a fabricated test vehicle in the frequency domain range up to 20 GHz, and it shows improved accuracy as well as computational superiority compared to EM simulations. Finally, the impedance properties in a chip-package hierarchical PDN are thoroughly investigated and analyzed.

A Compact and Wideband Electromagnetic Bandgap Structure Using a Defected Ground Structure for Power/Ground Noise Suppression in Multilayer Packages and PCBs

In this paper, we propose a compact and wideband electromagnetic bandgap (EBG) structure using a defected ground structure (DGS) to significantly enhance the wideband suppression of power/ground noise coupling in multilayer packages and printed circuit boards. The proposed EBG structure is implemented simply by adding a rectangular-shaped DGS which is etched periodically onto the ground plane without changing any other geometrical parameter from a mushroom-type EBG structure. The DGS effects on the fL and fU are thoroughly analyzed using the dispersion characteristics. We experimentally verified that the proposed EBG structure achieved the wideband power/ground noise suppression (below -40 dB) between 2.5 and 16.2 GHz. In addition, we demonstrated the considerable reduction in fL from 3.4 to 2.5 GHz and a significant increase in fU from 9.1 to 16.2 GHz when compared with the mushroom-type EBG structure.

A Compact and Wide-Band Passive Equalizer Design Using a Stub With Defected Ground Structure for High Speed Data Transmission

A compact wide-band passive equalization design using a stub with defected ground structure is proposed. The proposed design, based on reflections under a slow wave effect, compensates for inter-symbol interference with wide bandwidth, compact size, remarkable compensation capability with few manufacturing limitations, and high design flexibility, compared to previous equalization design. Significant improvements in eye-opening and timing jitter are successfully demonstrated for a data rate of 8 Gbps for a 60 cm transmission line on a printed circuit board.

Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package

A new hybrid modeling method is proposed for the chip-package co-modeling and co-analysis. This method is designed to investigate the simultaneous switching noise (SSN) coupling paths and effects on the dc output voltage offset of the operational amplifier (OpAmp). It combines an analytical model of the circuit with a power distributed network (PDN) and interconnection models at the chip and package substrate. In order to validate the proposed model, CMOS OpAmp was fabricated using TSMC 0.25 mum. Then the dc output offset voltage of the OpAmp was measured by sweeping the SSN frequency from 10 MHz up to 3 GHz. It was successfully demonstrated that the experimental results are consistent with the predictions generated using the proposed model. We also confirmed that the dc offset voltage is strongly dependent on the SSN frequency and the PDN impedance profile of the chip-package hierarchical PDN. It shows the necessity for the chip-package co-modeling and simulation of the system-in-package designs.

Modeling and Design Optimization of a Wideband Passive Equalizer on PCB Based on Near-End Crosstalk and Reflections for High-Speed Serial Data Transmission

We propose a closed-form analytic model for the newly presented passive equalizer using near-end crosstalk and reflections on printed circuit board (PCB). The proposed model is developed by using impulse response analysis and the Fourier transform. Based on the model, we propose a design-optimization procedure for the passive equalizer, which achieves eye-opening maximization and ISI minimization in order to maximize the equalization performance and reduce the design cycle. In the proposed optimization procedure, the eye-opening is maximized with a parameter sweep and peak distortion analysis, and the ISI is minimized by the proposed negative ISI cancellation technique. The proposed model and the design-optimization procedure are demonstrated experimentally for a data rate of 16 Gb/s on a 40-cm-long backplane PCB, and they achieve wideband equalization with a significant improvement in the voltage and timing margins of the received serial data.

An On-Chip Electromagnetic Bandgap Structure using an On-Chip Inductor and a MOS Capacitor

An on-chip electromagnetic bandgap (EBG) structure using a CMOS process is proposed. The proposed structure is the first EBG structure devised to suppress simultaneous switching noise coupling in an on-chip power distribution network (PDN). The on-chip EBG structure utilizes an on-chip inductor and a MOS capacitor to generate a stopband with a range of several GHz in an extremely small size; thus, the EBG structure can be embedded in on-chip PDNs. The proposed on-chip EBG structure was fabricated using a MagnaChip 0.18 μm CMOS process, and we successfully verified a 9.24 GHz stopband, from 1.26 to 10.5 GHz, with an isolation level of 50 dB.

Modeling and Analysis of Power Supply Noise Imbalance on Ultra High Frequency Differential Low Noise Amplifiers in a System-in-Package

In this paper, we analyze the power supply noise imbalance and its effects on simultaneous switching noise coupling to an ultra high frequency differential low noise amplifier (LNA) in a system-in-package (SiP) through an off-chip power distribution network (PDN). On and off-chip sources of power supply noise imbalance in a LNA in a SiP were analyzed. A simultaneous switching noise coupling coefficient for the differential LNA output caused by power supply noise imbalance was simulated through co-modeling a hierarchical on and off-chip PDN. The simulation results were validated by measuring the simultaneous switching noise coupling voltage at the differential LNA output. Further validation of four types of a LNA with different PDN designs demonstrates that simultaneous switching noise coupling to the differential LNA output caused by power supply noise imbalance highly depends on the design of the PDN of the SiP.

Wideband low power distribution network impedance of high chip density package using 3-D stacked through silicon vias

In this paper, we show the advantages of 3D stacked through silicon via (TSV) in high chip density package in aspect of wideband and low power distribution network (PDN) impedance. We selected large size (80 mum) and large pitch (200 mum) TSV with thick silicon substrate (Si, 80 mum, aspect ratio =1) for on-chip PDN, and compared two total PDN impedances of a PDN with TSVs and a PDN with wire-bondings depending on number of stacked chips from 2 to 10 on a single package. PDN impedance with TSVs includes total capacitance and inductance of TSV and 20 mm times 20 mm package substrate. PDN impedance with wire-bondings shows total capacitance and inductance of wire-bondings and same size package substrate. PDN impedance with TSVs has lower levels with wide bandwidth from 10 MHz to 5 GHz except serial resonance frequency range of the package substrate around 350 MHz. In low frequency range from 10 MHz to 350 MHz, total capacitance of a PDN with TSVs is larger than that of a PDN with wire-bonding because of 0.1 mum thickness silicon oxide (Si02) for blocking DC leakage from TSV to Si substrate. Over 350 MHz, total inductance of a PDN with TSVs is smaller than that of a PDN with wire-bonding because TSV is the smallest electrical path from top surface of stacked chips to the package PDN. The effectiveness of lowering total PDN impedance is better when the number of stacked chips is growing because total length of TSVs is linearly increased with factor 1 while total length of wire-bonding is done with factor radic(2).

Hybrid modeling and analysis of power supply noise effects on analog-to-digital converter considering hierarchical PDNs

An analog-to-digital converter (ADC) is an essential device in mixed mode systems. The performance of the ADC, however, is deteriorated by coupled power supply noises through hierarchical chip-PCB power distributed networks (PDNs). In order to design a high-performance system, modeling and analysis of power supply noise effects on the ADC are necessary, as the power supply noise is coupled to the circuit through the hierarchical PDN structure in multilayer PCB substrates. In this paper, a hybrid model is proposed for analysis of power supply noise effects on the ADC. The model combines two modeling mechanisms. First, the coupling ratio of the power supply noise is derived by the combined model of hierarchical PDNs at the PCB and the chip. Second, an analytical model is proposed using equivalent circuits for analysis of the power supply noise effects on the ADC. The ADC is designed using a 0.13um CMOS process. The proposed model and analysis are verified based on a simulation from 100kHz to 4GHz. The performance of the ADC is dominantly affected by characteristics of the on-chip circuit under 100MHz. It is also confirmed that the Effective Number of Bits (ENOB) of the ADC is strongly dependent on the hierarchical PDN impedance over 100MHz. Furthermore, there are peak points caused by inter-modulation (IMD) and cavity resonances of PDN structures.

A Wideband and Compact Partial Electromagnetic Bandgap Structure With a Narrow Via Pitch for a Signal Via Shield

A wideband and compact partial electromagnetic bandgap (PEBG) structure and a corresponding stopband-estimation model are proposed for the suppression of simultaneous switching noise (SSN) coupling in a multilayer printed circuit board. The proposed PEBG structure achieves a wide stopband with a compact size by adopting a geometric arrangement of patches that allows for a periodic narrow via pitch (NVP). In addition, the lumped capacitance model of the previously reported effective phase constant equation is replaced with the resonant cavity model to obtain the precise impedance of the patch in high frequency. Finally, it was successfully verified that, by applying the NVP-PEBG structure, wideband suppression of SSN coupling to the signal via is achieved with a bandwidth of 11.2 GHz below -40 dB. The proposed estimation model was validated through experimental measurements.