Jongjoo Shim

Active circuit to through silicon via (TSV) noise coupling

In this paper, we propose a coupling model between through silicon via (TSV) and substrate based on a 3-Dimensional transmission line matrix (3D-TLM), which utilizes equivalent lumped circuit model of silicon substrate and TSV. The proposed model is verified by S-parameter simulations using a 3D field solver and analyzed with various structural parameters: TSV diameter, distance between TSV and noise source, and silicon substrate height. Based on the model, timing jitter degradation on phase locked loop (PLL) caused by substrate noise coupling is investigated. A shielding technique using a guard ring structure is applied to suppress the coupling noise.

Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed. The key ideas of the proposed modeling method are to decompose the chip-package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structures impedance by using a segmentation method. For the impedance calculations of the independently decomposed structures, a new method based on proposed analytic expressions is introduced for a chip level PDN, a resonant cavity model is used for a package level PDN, and equivalent circuit models are used for interconnections. The proposed method has been successfully verified by comparisons with measurements using a fabricated test vehicle in the frequency domain range up to 20 GHz, and it shows improved accuracy as well as computational superiority compared to EM simulations. Finally, the impedance properties in a chip-package hierarchical PDN are thoroughly investigated and analyzed.

Circuital Modeling and Measurement of Shielding Effectiveness Against Oblique Incident Plane Wave on Apertures in Multiple Sides of Rectangular Enclosure

A simple circuital approach to evaluate the shielding effectiveness (SE) of rectangular enclosures with apertures is proposed, considering oblique incidence and polarization. The scope of the proposed model is extended beyond 1 GHz, including higher order modes of the cavity. Furthermore, apertures are not required to be on the front face of the enclosure. In the proposed model, the SE of the enclosure with apertures on multiple sides can be simply calculated by vector decomposition. The proposed model has been successfully verified by using a conventional full-wave simulation tool. We also measured the SE of a manufactured aluminum enclosure with apertures on multiple sides.

Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model

A hierarchical power distribution network (PDN) consists of chip, package, and printed circuit board (PCB) level PDNs, as well as various structures such as via, ball, and wire bond interconnections, which connect the different level PDNs. When estimating the simultaneous switching noise (SSN) generation and evaluating PDN designs, PDN impedance calculation is an efficient criterion. In this paper, we introduce two new kinds of modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation, especially for hierarchical PDN. First, we propose a modeling procedure to add an interlevel electromagnetic coupling effect between PDNs of different levels, based on the resonant cavity model and segmentation method. In order to effectively consider the interlevel electromagnetic coupling effect, we introduce a new concept of interlevel PDN, which is, for example, composed of a metal plate in the package-level PDN and a metal plate in the PCB-level PDN. Next, we present a modeling procedure to include the fringing field effect at the edge of small-size PDN structure, which causes a considerable shift of cavity resonance frequencies in the PDN impedance profile. In order to verify the proposed modeling approaches, we have fabricated a series of test vehicles by combining two package-level PDN designs with a PCB-level PDN design. Finally, we have successfully validated the proposed modeling approaches with a series of frequency-domain measurements in a frequency range up to 5 GHz.

An adaptive on-chip ESR controller scheme in power distribution network for simultaneous switching noise reduction

In this paper, we propose an adaptive on-chip equivalent series resistor (ESR) controller scheme to reduce on-chip simultaneous switching noise (SSN). The on-chip controllable ESR is adaptively changed to reduce the on-chip SSN by using the proposed scheme. Reduction of on-chip resonance and on-chip SSN is well proved through simulated results and measurements of the fabricated test chip in a 65 nm HYNIX CMOS process.

A precise analytical eye-diagram estimation method for non-ideal high-speed channels

In this paper, we propose an analytical eye-diagram estimation method for a channel of a pair of differential microstrip traces on PCBs with arbitrary source and load terminations. The closed-form equation of the voltage transfer function for the given channel structure is derived and the method to deduce the worst case data patterns by considering the asymmetric and finite slew rates of the input signals is introduced. The validity of the proposed method was verified through comparison with the DDJ and eye-opening voltage values obtained by using HSPICE simulations.

Modeling and Experimental Verification to Investigate the Effect of Power Supply Noise Imbalance on 900MHz Differential LNA

In this paper, the effect of power supply noise imbalance on 900 MHz differential low noise amplifier (LNA) output is investigated. Chip and package (PKG) power distribution network (PDN) are modeled with lumped components to estimate the power supply noise imbalance. Also an equivalent circuit of differential LNA is modeled to estimate the noise voltage at differential LNA output and verified through measurements. The results of this study reveal that the power supply noise imbalance is mainly caused by impedance resonances of PKG PDN and it directly coupled to the differential LNA output.

A 6.4Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel

In this paper, an on-chip eye opening monitor circuit has been proposed with 4 ps time and 4 mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4 Gbps data rate and give eye diagrams depending on on-chip high speed channel conditions. The performance of the proposed eye opening monitor circuit was verified by using a general Spice simulations and showed the variations of eye diagram of 6.4 Gbps random data when on-die terminations of on-chip high speed channel was changed from 50 ohm to 80 ohm.

Modeling of chip-package-PCB hierarchical power distribution network based on segmentation method

In this paper, a new modeling method for fast estimation of impedance profile in system-level PDN containing not only chip, package and PCB-level PDNs but also various interconnections such as via, ball and bond-wire is proposed. The basic modeling method is segmentation method and FDTD based EM solver and a series of analytic modeling methods such as resonant cavity model and lumped circuit model are used. The proposed modeling method is successfully verified by measurement up to 20 GHz in frequency domain.

Experimental verification and analysis for noise isolation of analog and digital chip-package-PCB hierarchical power distribution network

This paper presents and verifies a co-modeling and investigation approach of noise isolation analysis in hierarchical power distribution network (PDN) for low-noise 3D system-in-package (SiP) design. It is based on a hierarchical modeling to combine the lumped circuit models at both on-chip level PDN and off-chip level PDN. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z21 PDN impedance measurements with a frequency range from 1 MHz to 3 GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package-PCB hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the on-chip level PDN and the off-chip level PDN.