Jeongki Choi

A 5.8 GHz Integrated CMOS Dedicated Short Range Communication Transceiver for the Korea/Japan Electronic Toll Collection System

In this paper, a RF front-end of the 5.8 GHz integrated CMOS dedicated short range communication (DSRC) transceiver for the Korea/Japan electronic toll collection system is presented. The receiver uses low-IF conversion architecture for high sensitivity and low-power consumption while the transmitter uses direct up-conversion architecture for its simple structure and reliability. To solve image problem in the low-IF receiver, 10 MHz IF and 40 MHz IF are chosen for Korean and Japanese DSRC standards, respectively, since they make no image signals exist in image band. A single-quadrature mixer with the proposed transconductor-type quadrature generator in RF signal path is also adopted which has accurate quadrature characteristic in 5.8 GHz frequency. When the RF front-end of the integrated 5.8 GHz DSRC transceiver is implemented using 0.13 μm CMOS technology, the receiver achieves the overall noise figure of less than 5 dB with image rejection ratio of more than 30 dB, and the transmitter carries an output peak power of 10 dBm with the adjacent channel power ratio of -43 dBc. The RF front-end of the 5.8 GHz DSRC transceiver dissipates 45 mA with 1.2 V supply voltage and 142 mA with 1.2/3.3 V dual supply voltage during RXand TX-modes, respectively.

An interference-aware 5.8GHz wake-up radio for ETCS

Wake-up radios have been a popular transceiver architecture in recent years for battery-powered applications such as wireless body area networks (WBANs) [1], wireless sensor networks (WSNs) [2,3], and even electronic toll collection systems (ETCS) [4]. The most important consideration in implementing a wake-up receiver (WuRX) is low power dissipation while maximizing sensitivity. Because of this requirement of very low power, WuRX are usually designed by a simple RF envelope detector (RFED) consisting of Schottky diodes [1,3] or MOSFETs in the weak inversion region [2] without active filtering or amplification of the input signal. Therefore, the performance of the RFED itself is critical for attaining good sensitivity of the WuRX. Moreover, the poor filtering of the input signal renders the WuRX vulnerable to interferers from nearby terminals with high transmit power such as mobile phones and WiFi devices, and this can result in false wake-ups [1]. Although the RFED has very low power, a false wake-up will increase the power consumption of the wake-up radio as it will enable the power-hungry main transceiver.

Radio specifications of double conversion tuner for cable modem

The radio specifications such as noise figure, phase noise, image rejection ratio, CTB, CSO, XMOD, power gain, and AGC range of the tuner for cable modem is analyzed based on DOCSIS and many reported materials. Using the analyzed radio specifications, the specific radio specifications are allocated for up and down converter of the DC tuner architecture and analyzed CTB and CSO requirement in depth. According to the linearity analysis for the DC tuner architecture, it is known that CTB and CSO value of -53dBc, which is commonly accepted by the field engineer, is over-specified. By the more reasonable selection of linearity target, it is possible to design DC tuner with better power efficiency.

A UHF-band RFID transmitter with spur reduction technique using a DLL-based spread-spectrum clock generator

This paper presents a UHF-band RFID transmitter with a robust spur reduction technique using a DLL-based SSCG. By adopting an 8-bit DLL and Hershey-kiss modulated profile together, the SSCG shows more than a 20dB EMI reduction while providing up-, down-, and center-spread modes. Implemented in a 0.18μm CMOS process, the proposed transmitter achieves <; -80dBc spur suppression with 25dBm transmit power at 920MHz, which complies with the most stringent regulatory spectral mask without a SAW-filter.

A 5.8-GHz DSRC Transceiver With a 10-

This paper presents a fully integrated 5.8-GHz dedicated short-range communication transceiver with a 10- μA interference-aware wake-up receiver (WuRx) for Chinese electronic toll collection system terminals that can operate with a low standby and operating current consumption. To reduce the current consumption, a high-gain RF envelope detector using a voltage-boosting method is proposed for both the WuRx and receiver (Rx) while the proposed high-power ASK modulator extends output dynamic range in low power consumption. Additionally, a delay-based bandpass filter is adopted in the WuRx to filter out interference from automotive applications, thus increasing the battery lifetime by reducing the probability of a false wake-up. The proposed transceiver is fabricated using 0.13- μm CMOS technology with a chip size of 2.8 mm2 for the target frequency range of 5.8 GHz. The measured results demonstrate sensitivities of -44 and -61 dBm for the WuRx and Rx, dissipating currents of 10 μA and 19 mA from 3.3-V supply voltage, respectively. The transmitter exhibits a normal output power of +5 dBm at an operating current of 46 mA.

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A very high-Q poly-to-poly capacitor structure and the measurement results are presented. The poly-to-poly capacitor is designed on a conventional 0.35 /spl mu/m CMOS process. Through the layout optimization, a Q-factor greater than 120 is obtained at 2 GHz.

Interference-Aware Wake-Up Receiver for the Chinese ETCS

This paper presents a robust spur reduction technique using a switched-capacitor feedback differential phase-locked loop (PLL) and a delay-locked-loop (DLL)-based spread-spectrum clock generation in a UHF-band RF identification transmitter (TX). The proposed differential PLL is characterized by adopting a switched-capacitor common-mode feedback and distributed varactor biasing scheme to the differential charge pump and voltage-controlled oscillator designs, respectively, which results in down to 94 dBc in reference spur rejection with all digital parts off. Additionally, by adopting an 8-bit DLL and Hershey-Kiss modulated profile together, the proposed spread-spectrum clock generator shows more than 20-dB electromagnetic-interference reduction while providing up-, down-, and center-spread modes. Implemented in a 0.18m CMOS process, the proposed TX achieves <; - 80-dBc spur suppression with 25-dBm transmit power at 920 MHz, which complies with the most stringent regulatory spectral mask without a surface acoustic wave filter.

High-Q poly-to-poly capacitor design for RF applications

A dual-band receiver architecture for PCS and IMT-2000 is described. The proposed architecture is suitable for high-level integration and minimizes the hardware duplicity by adopting a single wide-band high-performance image-rejection mixer in conjunction with a frequency doubler. Along with the architectural aspects of the dual-band receiver, the circuit implementation details are described.

Spur Reduction Techniques With a Switched-Capacitor Feedback Differential PLL and a DLL-Based SSCG in UHF RFID Transmitter

In TV tuner systems, the RF front-end design has been a challenging issue since it must simultaneously satisfy over 65dB of harmonic rejection (HR), and have high linearity for high-power input and low noise over wide bandwidth (48-to-870MHz). In terms of harmonic rejection, even though the state-of-the-art work reports over 60dB rejections on the 3rd- and 5th- order harmonics with a single mixer [1], higher-than-5th-order harmonic rejections are still required for the low-band channels in TV tuners and thereby RF filters are indispensable at the RF front-end. However, due to the difficulties of integrating RF filters satisfying low noise and high linearity over wide bandwidth, the previous works inevitably had to use external inductors [2-4]. Although a recent work successfully integrates an RF filter satisfying all the stringent specifications by current-domain signal flow from the LNA output to the baseband stage [5], the transconductance stage at the filter input is not linear enough to drive the high-power input and thus the input signal needs to be attenuated at the RF front-end, which eventually degrades system SNR.

A dual-band receiver architecture for PCS and IMT-2000

This paper presents a switching PA-based polar transmitter which achieves uniform and robust performances under process, voltage, and temperature variations. A new approach utilizing current driven envelope signal is proposed, leading to much more accurate control of output power of the PA. In addition, the proposed adaptive LO technique extends the available linear control range of the PA. Fabricated in 0.13 um CMOS process, an experimental polar transmitter is designed to fulfill the stringent requirements of the 5.8 GHz Korean DSRC/ETC standards. Delivering output power of + 12 dBm, it consumes average current of 35 mA at 3.3 V supply voltage. Output P-1dB of 15 dBm and ACPR lower than −50 dBc are obtained. The transmitter achieves output power error less than ± 1 dB over the temperature and supply voltage range from −40 to 100 °C and from 3.0 to 3.6 V.