Choong-Yul Cha

A very low-power quadrature VCO with back-gate coupling

A new quadrature voltage-controlled oscillator (QVCO) topology is proposed where the back-gates of the core transistors are used as coupling terminals. The use of back-gates reduces the power dissipation and removes the additional noise contributions compare to the conventional coupling transistor based topology. The advantages of the proposed QVCO topology in comparison with prior works are exploited based on simulation. A QVCO based on the proposed topology with additional design ideas has been implemented using a 0.18-/spl mu/m triple-well technology for 1 GHz-band operation, and measurement shows the phase noise of -120 dBc/Hz at 1-MHz offset with output power of 2.5 dBm, while dissipating only 3 mA for the whole QVCO from 1.8-V supply.

A 5.2-GHz LNA in 0.35-/spl mu/m CMOS utilizing inter-stage series resonance and optimizing the substrate resistance

A current-reused two-stage low-noise amplifier (LNA) topology is proposed, which adopts a series inter-stage resonance and optimized substrate resistance of individual transistors. The characteristics of the series inter-stage resonance in gain enhancement are analyzed and compared with other alternatives. The contradicting effects of substrate resistance on common-source and common-gate amplifiers are analyzed and proposed guidelines for high-gain operation. The LNA is implemented based on a 0.35-/spl mu/m CMOS technology for 5.2-GHz wireless LAN applications. Measurements show 19.3dB of power gain, 2.45 dB of noise figure, and 13.2 dBm of output IP3, respectively, for the dc power supply of 8 mA and 3.3 V.

Image-rejection CMOS low-noise amplifier design optimization techniques

This paper reviews and analyzes two reported image-rejection (IR) low-noise amplifier (LNA) design techniques based on CMOS technology, i.e., the second-order active notch filer and third-order passive notch filter. The analyses and discussions are based on the quality factor of filters and the ability of the frequency control. As the solution to deal with the suitable on-chip filter, this paper proposes a new notch-filter topology that can overcome the limitations of the two previous reported studies. In addition, the LNA design method satisfying the power-cons-trained simultaneous noise and input matching, as well as the linearity optimization conditions is introduced. By using the proposed notch filter and proposed design methodology, an IR LNA used in the superheterodyne architecture is implemented. The proposed IR LNA, designed based on 0.18-mum CMOS technology with total current dissipation of 4 mA under 3-V supply voltage, is optimized for a 5.25-GHz wireless local area network with IF frequency of 500-MHz applications. The measurement results show 20.5-dB power gain, lower than 1.5-dB noise figure, -5-dBm input-referred third-order intercept point and an IR of 26 dB

A complementary Colpitts oscillator in CMOS technology

A new complementary Colpitts (C-Colpitts) oscillator topology is introduced and the oscillation mechanism as a one-port model is analyzed. Based on the one-port analysis and the existing phase-noise model, the phase-noise equation of the proposed C-Colpitts oscillator is derived as the function of the oscillation frequency, Q factor of tank circuit, and bias current. The phase-noise equation provides the design guideline to optimize the phase noise of the proposed Colpitts oscillator, of which the property is proven with simulation and measurement results. The proposed Colpitts voltage-controlled oscillators are fabricated using 0.35-/spl mu/m CMOS technology for 2-, 5-, 6-, and 10-GHz bands. Measurement shows that the phase noise is -118.1 dBc at 1-MHz offset from 6-GHz oscillation while dissipating 4.6 mA of current from a 2.0-V supply.

A low power, high gain LNA topology

A novel high gain and low noise amplifier topology is proposed. The proposed LNA topology is a current sharing two-stage cascade amplifier adopting a series inter-stage resonance. The performance of the proposed topology is compared with the existing high gain amplifiers, qualitatively and quantitatively. The simulation results at 2.4 GHz based on 0.35 /spl mu/m CMOS technology are also provided. The proposed topology demonstrates excellence over the existing high gain topologies in gain and noise figure.

RF CMOS differential oscillator with source damping resistors

This paper proposes a new method to suppress the 1/f noise contribution of active devices in an oscillator using source damping resistors. The operational mechanism of the proposed method is analyzed through circuit simulation with a complementary LC differential oscillator topology. This shows that the amount of 1/f noise and the mismatch of instantaneous current swing of the oscillator active devices can be substantially reduced with source damping resistors. The reduced 1/f noise and instant current mismatch leads to a phase noise improvement by suppressing 1/f noise up-conversion to phase noise. To prove experimentally the usability of the proposed technique, two complementary LC differential VCOs with different damping conditions are fabricated using 0.18 /spl mu/m CMOS technology. The measurement result shows that there is about 6.0 dBc, 4.0 dBc and 1.0 dBc of phase noise improvement at 10 kHz, 100 kHz and 1 MHz offset frequency with source damping resistors, respectively.

Radio specifications of double conversion tuner for cable modem

The radio specifications such as noise figure, phase noise, image rejection ratio, CTB, CSO, XMOD, power gain, and AGC range of the tuner for cable modem is analyzed based on DOCSIS and many reported materials. Using the analyzed radio specifications, the specific radio specifications are allocated for up and down converter of the DC tuner architecture and analyzed CTB and CSO requirement in depth. According to the linearity analysis for the DC tuner architecture, it is known that CTB and CSO value of -53dBc, which is commonly accepted by the field engineer, is over-specified. By the more reasonable selection of linearity target, it is possible to design DC tuner with better power efficiency.

A fast frequency/mode switching quadrature SSB mixer/amplifier for the low power MTG in MB-OFDM UWB radio transceiver

A fast frequency/mode switching SSB mixer/amplifier topology is proposed for the implementation of low power multi-tone generator (MTG) in MB-OFDM UWB system. The proposed SSB mixer/amplifier topology is fabricated for the generation of mode-1 band center carrier with 0.18mum CMOS technology. The measurement result shows the 8.5ns mixer/amplifier mode switching time. The center carrier output power levels are -13.0dBm, -12.88dBm, and -14.33dBm in 3432MHz, 3960MHz, and 4488MHz, respectively. The harmonic suppressions are -40dBc and -30dBc in 3432MHz and 4488MHz, where the SSB mixer mode is selected. In the amplifier mode, the 3960MHz tone does not have any harmonics tone. For measurement, 1.8V supply voltage is used while drawing 26mA total current

A Source Coupled Differential CMOS Complementary Colpitts Oscillator With On-Chip Transformer Tank

A source coupled differential CMOS complementary Colpitts (C-Colpitts) oscillator with an on-chip transformer tank is proposed. Additionally, the on-chip transformer is analyzed through electromagnetic simulation, and the equivalent circuit is modeled with lumped components. The Q factor of an on-chip transformer is compared with symmetrical inductors, which have almost the same inductance. The proposed source coupled differential C-Colpitts oscillator is fabricated with 0.18-mum CMOS technology. With 1.4-V supply voltage, the oscillator shows phase noise of -145.6 dBc at 3-MHz offset in 1.8-GHz oscillation frequency.

A complementary Colpitts oscillator based on 0.35 /spl mu/m CMOS technology

A new complementary Colpitts CMOS oscillator topology is proposed and analyzed based on one port model. Analysis indicates that the proposed complementary Colpitts oscillator topology has advantage over other topologies for low phase noise and high frequency operation while the design guidelines for optimizing the phase noise of the proposed topology. The performance advantage of proposed oscillator topology originates from the simplicity, composed of effectively only two components (complementary transistor and one inductor), and the higher negative conductance of oscillator core. The proposed VCOs are fabricated using the 0.35/spl mu/m CMOS technology for 2, 5, 6 and 10GHz band. Measurement shows excellent performance considering the technology and power dissipation in 5 and 6 GHz band VCOs.