Jinho Ko

A 19-mW 2.6-mm/sup 2/ L1/L2 dual-band CMOS GPS receiver

This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. Dual-conversion with a low-IF architecture was used for dual-band operation. The receiver is composed of an RF preamplifier, down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and the full phase-locked-loop synthesizer including an on-chip voltage controlled oscillator. Fabricated in a 0.18-/spl mu/m CMOS technology, the receiver exhibits maximum gain of 95 dB and noise figures of 8.5 and 7.5 dB for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection of 20 dB and gain control range over 60 dB. The receiver consumes 19 mW from a 1.8-V supply while occupying a 2.6-mm/sup 2/ die area including the ESD I/O pads.

A CMOS 868/915 MHz direct conversion. ZigBee single-chip radio

In this article the 868/915 MHz radio transceiver specifications have been derived for IEEE 802.15.4, a low-rate, low-cost, and low-power network standard. The radio specifications include parameters such as noise figure, nonlinearity, channel filtering, phase noise of local oscillator, dynamic range, and bit resolutions of analog-to-digital and digital-to-analog converters. Based on a direct conversion scheme, top-down system-level performance analyses using the radio specifications are realized. Low-power and low-cost circuit topologies are also discussed with chip implementations using 0.18 pm CMOS technology.

A 5.8 GHz Integrated CMOS Dedicated Short Range Communication Transceiver for the Korea/Japan Electronic Toll Collection System

In this paper, a RF front-end of the 5.8 GHz integrated CMOS dedicated short range communication (DSRC) transceiver for the Korea/Japan electronic toll collection system is presented. The receiver uses low-IF conversion architecture for high sensitivity and low-power consumption while the transmitter uses direct up-conversion architecture for its simple structure and reliability. To solve image problem in the low-IF receiver, 10 MHz IF and 40 MHz IF are chosen for Korean and Japanese DSRC standards, respectively, since they make no image signals exist in image band. A single-quadrature mixer with the proposed transconductor-type quadrature generator in RF signal path is also adopted which has accurate quadrature characteristic in 5.8 GHz frequency. When the RF front-end of the integrated 5.8 GHz DSRC transceiver is implemented using 0.13 μm CMOS technology, the receiver achieves the overall noise figure of less than 5 dB with image rejection ratio of more than 30 dB, and the transmitter carries an output peak power of 10 dBm with the adjacent channel power ratio of -43 dBc. The RF front-end of the 5.8 GHz DSRC transceiver dissipates 45 mA with 1.2 V supply voltage and 142 mA with 1.2/3.3 V dual supply voltage during RXand TX-modes, respectively.

An interference-aware 5.8GHz wake-up radio for ETCS

Wake-up radios have been a popular transceiver architecture in recent years for battery-powered applications such as wireless body area networks (WBANs) [1], wireless sensor networks (WSNs) [2,3], and even electronic toll collection systems (ETCS) [4]. The most important consideration in implementing a wake-up receiver (WuRX) is low power dissipation while maximizing sensitivity. Because of this requirement of very low power, WuRX are usually designed by a simple RF envelope detector (RFED) consisting of Schottky diodes [1,3] or MOSFETs in the weak inversion region [2] without active filtering or amplification of the input signal. Therefore, the performance of the RFED itself is critical for attaining good sensitivity of the WuRX. Moreover, the poor filtering of the input signal renders the WuRX vulnerable to interferers from nearby terminals with high transmit power such as mobile phones and WiFi devices, and this can result in false wake-ups [1]. Although the RFED has very low power, a false wake-up will increase the power consumption of the wake-up radio as it will enable the power-hungry main transceiver.

L1/L2 dual-band CMOS GPS receiver

This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. The receiver has been implemented in a 1P6M 0.18 /spl mu/m CMOS technology. It consists of a low-noise pre-amplifier, I-Q mixers, VGA-merged complex BPFs, 2-bit analog-digital converters, and a whole phase-locked loop synthesizer, excluding loop filter. The measured results show 95-dB maximum gain, 8.5-dB noise figure and -31-dBm IIP3 while consuming 10.6 mA from a 1.8 V supply voltage.

An isolator-less CMOS RF front-end for UHF mobile RFID reader

RFID systems are based on backscattering communications, and this encourages research on how to guarantee a reliable RX performance under simultaneous TX/RX operation. To isolate RX from the TX self-jammer, the RFID transceivers are generally accompanied by an off-chip circulator or isolator. This has advantages in selectivity between tag signal and blocker, but it results in a low level of integration and bulky system [1,2,4]. In addition, to meet the stringent linearity requirement, the RFID reader needs to adopt a linear PA with sufficient power back-off, which degrades a global efficiency. Considering that battery life time is the critical issue particularly for mobile applications, existing UHF RFID readers are unsuitable for the mobile RFID technology due to their low system efficiency and low integration level.

A UHF-band RFID transmitter with spur reduction technique using a DLL-based spread-spectrum clock generator

This paper presents a UHF-band RFID transmitter with a robust spur reduction technique using a DLL-based SSCG. By adopting an 8-bit DLL and Hershey-kiss modulated profile together, the SSCG shows more than a 20dB EMI reduction while providing up-, down-, and center-spread modes. Implemented in a 0.18μm CMOS process, the proposed transmitter achieves <; -80dBc spur suppression with 25dBm transmit power at 920MHz, which complies with the most stringent regulatory spectral mask without a SAW-filter.

A 5.8-GHz DSRC Transceiver With a 10-

This paper presents a fully integrated 5.8-GHz dedicated short-range communication transceiver with a 10- μA interference-aware wake-up receiver (WuRx) for Chinese electronic toll collection system terminals that can operate with a low standby and operating current consumption. To reduce the current consumption, a high-gain RF envelope detector using a voltage-boosting method is proposed for both the WuRx and receiver (Rx) while the proposed high-power ASK modulator extends output dynamic range in low power consumption. Additionally, a delay-based bandpass filter is adopted in the WuRx to filter out interference from automotive applications, thus increasing the battery lifetime by reducing the probability of a false wake-up. The proposed transceiver is fabricated using 0.13- μm CMOS technology with a chip size of 2.8 mm2 for the target frequency range of 5.8 GHz. The measured results demonstrate sensitivities of -44 and -61 dBm for the WuRx and Rx, dissipating currents of 10 μA and 19 mA from 3.3-V supply voltage, respectively. The transmitter exhibits a normal output power of +5 dBm at an operating current of 46 mA.

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The measurement system for healthcare signals such as heart rate and body temperature is significantly important to prevent and monitor of potential heart attack. Although numerous researchers have developed wearable devices and systems, there are still lots of issues to be solved to expand their applications. To overcome such issues, we propose the new types of healthcare-on-a-patch using flexible PCB and flexible battery. This patch system could measure and transmit the physiological signal on body skin. The heart rate and the body temperature were excellently monitored in Bluetooth wireless communication. Furthermore, it was flexible enough to be rolled in a small barrel while working.

Interference-Aware Wake-Up Receiver for the Chinese ETCS

This paper presents a robust spur reduction technique using a switched-capacitor feedback differential phase-locked loop (PLL) and a delay-locked-loop (DLL)-based spread-spectrum clock generation in a UHF-band RF identification transmitter (TX). The proposed differential PLL is characterized by adopting a switched-capacitor common-mode feedback and distributed varactor biasing scheme to the differential charge pump and voltage-controlled oscillator designs, respectively, which results in down to 94 dBc in reference spur rejection with all digital parts off. Additionally, by adopting an 8-bit DLL and Hershey-Kiss modulated profile together, the proposed spread-spectrum clock generator shows more than 20-dB electromagnetic-interference reduction while providing up-, down-, and center-spread modes. Implemented in a 0.18m CMOS process, the proposed TX achieves <; - 80-dBc spur suppression with 25-dBm transmit power at 920 MHz, which complies with the most stringent regulatory spectral mask without a surface acoustic wave filter.