Jeongpyo Park

A CCM/DCM Dual-Mode Synchronous Rectification Controller for a High-Efficiency Flyback Converter

A dual-mode synchronous rectification (SR) controller supporting both the continuous-conduction mode and discontinuous-conduction mode is developed to improve the power efficiency of a flyback converter. The dual-mode SR controller ensures nonoverlapped turning-on of the primary and secondary switches by monitoring the voltage level of the secondary switch. The dual-mode SR controller requiring four pins and only one external resistor has been implemented in a 0.35-μm BCDMOS process and applied to a 50-W flyback converter. The efficiency of the flyback converter is improved by upto 6.8% when the dual-mode SR controller is employed compared to the one employing the conventional SR controller.

A Two-Phase Interleaved Power Factor Correction Boost Converter With a Variation-Tolerant Phase Shifting Technique

This paper presents a two-phase interleaved critical conduction mode (CRM) power factor correction boost converter with a variation-tolerant phase shifter (VTPS), which ensures accurate 180° phase shift between the two interleaved converters. A feedback loop similar to a phase-locked loop controls the amount of the phase shifting of the VTPS. The proposed VTPS has better immunity of process, supply, and temperature variations than the conventional phase shifter. A 320-W two-phase interleaved CRM boost converter prototype has been implemented, while the proposed VTPS and conventional interleaving phase shifter can be selectively applied to compare the performance of the proposed technique with the conventional one. Experimental results show that the two-phase interleaved CRM boost converter has better performance with the proposed VTPS. The proposed VTPS circuit can be applied to any type of interleaved switching power converter.

A Multiphase Synchronous Buck Converter With a Fully Integrated Current Balancing Scheme

A multiphase synchronous buck converter has been developed, in which the number of switching phases is determined by the sensed average load current. The maximum number of switching phases is four. The dc resistance (DCR) of switching inductor is used to detect the average current, which is also utilized to balance the load current among the multiple switching phases. The instantaneous inductor current is sensed as well to generate the pulsewidth modulation (PWM) signal to switch the inductors. The multiphase synchronous buck converter implemented in a 0.13-μm BCDMOS process shows 91.1% maximum power efficiency when the input voltage is 2.8 V, output voltage is 1.0 V, and output current is 2.0 A.

Wireless power charger for wearable medical devices with in-band communication

Summary A wireless power charger integrated circuit has been developed for wearable medical devices in a 0.18-µm Bipolar, Complementary metal-oxide-semiconductor, and Lightly-Doped Metal-Oxide-Semiconductor (BCDMOS) process. A passive full-wave rectifier consisting of Schottky diodes and cross-coupled n-type Metal-Oxide-Semiconductor (nMOS) transistors performs the alternating current to direct current power conversion without any reverse leakage current. To charge a battery, a linear charger circuit follows the passive rectifier instead of a switching charger circuit for the small form factor of wearable medical devices. An in-band communication circuit notifies the proper connection of the wireless power receiver and the battery charging status to the charging pad (wireless power transmitter) through the wireless power transmission channel. The wireless power charger integrated circuit occupies 1.44-mm2 silicon area and shows 31.7% power efficiency when the charging current is 26.6 mA. Copyright

Quasi-Resonant (QR) Controller With Adaptive Switching Frequency Reduction Scheme for Flyback Converter

A quasi-resonant (QR) controller with an adaptive frequency reduction scheme has been developed for a flyback converter. While maintaining the valley switching, the QR controller reduces the switching frequency for lighter load by skipping some valleys to reduce the power loss and thereby achieve better light-load efficiency. If the QR controller cannot detect any valley due to the damped oscillation of switch voltage, then the valley switching is given up and the nonvalley switching is employed to keep reducing the switching frequency for lighter load. The proposed QR controller has been implemented in a 0.35-μm 700-V BCDMOS process and applied to a 40-W flyback converter. The power efficiency of the flyback converter is improved by up to 3.0% when the proposed QR controller is employed compared to the one employing the conventional QR controller.

Low Drop-Out (LDO) Voltage Regulator with Improved Power Supply Rejection

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-µm standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38- dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-�A.

A 40-W Flyback Converter with Dual-Operation Modes for Improved Light Load Efficiency

A flyback converter operates with either pulse width modulation (PWM) or pulse frequency modulation (PFM) control scheme depending on the load current. At light load condition, PFM control is employed to reduce the switching frequency and thereby minimize the switching power loss. For heavier load, PWM control is used to regulate the output voltage of the flyback converter. The flyback controller has been implemented in a 0.35 μm BCDMOS process and applied to a 40-W flyback converter. The light-load power efficiency of the flyback converter is improved up to 5.7-% comparing with the one operating with a fixed switching frequency.