Jeongwook Kim

ULP-SRP: Ultra Low-Power Samsung Reconfigurable Processor for Biomedical Applications

The latest biomedical applications require low energy consumption, high performance and wide energy-performance scalability to adapt to various working environments. This paper presents ULP-SRP, an energy efficient reconfigurable processor for the biomedical applications. ULP-SRP uses a Coarse Grained Reconfigurable Array (CGRA) for high performance data processing with low energy consumption. For the scalability, we propose three performance modes and Unified Memory Architecture (UMA). Energy optimization is accomplished by run-time mode switching along with automatic power gating. Experimental results show that ULP-SRP achieved 46.1% energy reduction compared to previous works.

Design space exploration and implementation of a high performance and low area Coarse Grained Reconfigurable Processor

Coarse Grained Reconfigurable Architectures (CGRAs) have played a key role in the area of domain specific processors due to their programmability and runtime reconfigurability. The Coarse Grained Array (CGA) structure enables target designs to achieve high performance, but it is easy to fall into over-design in term of area. Moreover, the network overhead between the function units (FUs) seriously degrades its clock speed. In this paper, we propose a high performance CGRA that facilitates design space exploration (DSE) to reduce these overheads. It employs a concept of building blocks, named mini cores, to mitigate overhead involved in DSE that aims to achieve high clock speed and small area in the target design. The proposed approach reduces the design time more than 100 times compared with previous design. Experimental results show that the implemented architecture reduces logic area by 14.38% and improves clock frequency by 59.34% without performance loss.

Real-time ray tracing on future mobile computing platform

In this work, we present a novel mobile computing platfom for mobile ray tracing in which a fast compact hardware accelerator and a flexible programmable shader are combined. Our platform has two key features: 1) an area-efficient parallel pipelined traversal unit; and 2) flexible and high-performance kernels for shading and ray generation. Simulation results show that our platform is potentially a versatile graphics solution for future application processors as it provides a real-time ray tracing performance at full HD resolution that can compete with that of existing desktop GPU ray tracers. Our system is implemented on an FPGA platform, and mobile ray tracing is successfully demonstrated.

Real-time ray tracing on coarse-grained reconfigurable processor

Ray tracing is a 3D rendering method for generating an image by simulating the path of light. It can generate high quality images, but it requires great computing power. Recent advances in ray tracing technology enable realtime ray tracing on modern desktop CPUs/GPUs. But in the current mobile environment, it is difficult because of inadequate computing power, memory bandwidth, and flexibility in mobile GPUs. In this paper, we present a mobile ray tracing system using Samsung Reconfigurable Processor (SRP). SRP architecture includes a tightly coupled very long instruction word (VLIW) engine and coarse-grained reconfigurable array (CGRA). The VLIW engine is designed for general-purpose computations, such as function invocation and branch selection, and the coarsegrained reconfigurable array is specialized for data-intensive part of the program and can be configured dynamically. We proposed iterative batch-based ray tracing algorithm for SRP, and optimized memory bandwidth with local memory and data cache. Our ray tracing system is implemented on a commercial FPGA-based prototyping system. The experimental results show that our system is suitable for the mobile ray tracing.

Two-AABB traversal for mobile real-time ray tracing

Ray tracing is a 3D rendering method which simulates the path of light. This technique can represent high quality visual realism, but it requires great computing power. Because of the insufficient computing power in mobile device, some hardware accelerator is required for mobile real-time ray tracing. In this work, we propose a novel hardware unit which has two-AABB (Axis Aligned Bounding Box) traversal architecture. Our architecture has two ray-AABB testing units and the efficient leaf node processing mechanism. The experimental results show that our hardware architecture has half the gate count and is up to 2.9 times faster than the existing single pipeline architecture.

An energy efficient hardware multithreading scheme for mobile ray tracing

We present an energy-efficient multithreading architecture for mobile ray tracing, which constitutes a dynamic reordering of the rays in input buffer according to the results of cache accesses. Unlike to the previous works, our architecture is cost-effective, because it does not need dedicated memory for storing threads, and is also energy-efficient, because it does not bypass the invalidated rays. Simulation results show that our architecture is a potential graphics solution for low-power ray tracing hardware as it provides a better performance-energy efficiency up to 5.5 times that of previous architectures.

Energy efficient data transmission for ray tracing on mobile computing platform

In this paper, we focus the impact of a memory bandwidth limitation by analyzing the bandwidth consumption for ray tracing system and present an energy efficient data transmission method between processor and ray tracing hardware engine. For evaluation of our approach, we have implemented a prototype of ray tracing architecture using our approach on FPGA platform. According to our experiment result, our approach shows a 48% reduction of system memory bandwidth on average.

Full-stream architecture for ray tracing with efficient data transmission

In this paper, we focus on the impact of a memory bandwidth limitation by analyzing the bandwidth consumption for a ray tracing system and present an energy efficient data transmission method using a dedicated interface between the processor and ray tracing hardware engine. To achieve real-time ray tracing, we propose a full-stream architecture through the use of this dedicated interface. For an evaluation of our approach, we implemented a prototype ray tracing architecture using our approach on an FPGA platform. Our experimental results, indicate that our approach shows an average reduction in system memory bandwidth of 48% and an average performance improvement of 50%.

Path rendering using winding number generator

In this paper, we propose a computing intensive path rendering scheme. Because legacy path rendering schemes are memory I/O bound they are not suitable to the high resolution display. To do so, we propose to use winding number generator which generates per pixel winding number in parallel manner. When we use the winding number generator, computing latency (cycles) for path rendering are reduced into about 22%.

Path rendering for high resolution mobile device

In this paper, we present a novel path rendering scheme that provides a fast rendering on high resolution mobile device. Because legacy path renderings are memory intensive work, they do not provide enough performance (fps) on high resolution display. To get an acceptable performance, we propose a novel approach for path rendering. Our design policies for the path rendering are two folds: 1) Minimize memory I/O, 2) Highly parallel computational scheme. We propose to use winding number generator for per-pixel winding number calculation which does not require memory intensive activity. Because our scheme effectively reduces memory I/O and it is executed with highly parallel manner, we can get an acceptable high performance on high resolution mobile device.