Seok Joong Hwang

Two-AABB traversal for mobile real-time ray tracing

Ray tracing is a 3D rendering method which simulates the path of light. This technique can represent high quality visual realism, but it requires great computing power. Because of the insufficient computing power in mobile device, some hardware accelerator is required for mobile real-time ray tracing. In this work, we propose a novel hardware unit which has two-AABB (Axis Aligned Bounding Box) traversal architecture. Our architecture has two ray-AABB testing units and the efficient leaf node processing mechanism. The experimental results show that our hardware architecture has half the gate count and is up to 2.9 times faster than the existing single pipeline architecture.

Reorder buffer: an energy-efficient multithreading architecture for hardware MIMD ray traversal

In this paper, we present an energy- and area-efficient multithreading architecture for Multiple Instruction, Multiple Data (MIMD) ray tracing hardware targeted at low-power devices. Recent ray tracing hardware has predominantly adopted an MIMD approach for efficient parallel traversal of incoherent rays, and supports a multithreading scheme to hide latency and to resolve memory divergence. However, the conventional multithreading scheme has problems such as increased memory cost for thread storage and consumption of additional energy for bypassing threads to the pipeline. Consequently, we propose a new multithreading architecture called Reorder Buffer. Reorder Buffer solves these problems by constituting a dynamic reordering of the rays in the input buffer according to the results of cache accesses. Unlike conventional schemes, Reorder Buffer is cost-effective and energy-efficient because it does not need additional thread memory nor does it consume more energy because it makes use of existing resources. Simulation results show that our architecture is a potentially versatile solution for future ray tracing hardware in low-energy devices because it provides as much as 11.7% better cache utilization and is up to 4.7 times more energy-efficient than the conventional architecture.

An energy efficient hardware multithreading scheme for mobile ray tracing

We present an energy-efficient multithreading architecture for mobile ray tracing, which constitutes a dynamic reordering of the rays in input buffer according to the results of cache accesses. Unlike to the previous works, our architecture is cost-effective, because it does not need dedicated memory for storing threads, and is also energy-efficient, because it does not bypass the invalidated rays. Simulation results show that our architecture is a potential graphics solution for low-power ray tracing hardware as it provides a better performance-energy efficiency up to 5.5 times that of previous architectures.

A mobile ray tracing engine with hybrid number representations

This paper presents optimization techniques devised to a hardware ray tracing engine which has been developed for mobile platforms. Whereas conventional designs deal with either fixed-point or floating-point numbers, the proposed techniques are based on hybrid number representations with fixed-point and floating-point ones. Carefully mixing the two heterogeneous number representations in computation and value encoding could improve efficiency of the ray tracing engine in terms of both energy and silicon area. Compared to a floating-point-based design, 35% and 16% area reduction was achieved in ray-box and ray-triangle intersection units, respectively. In addition, such hybrid representation could encode a bounding box in 40% smaller space at a reasonably low cost.

An efficient hybrid ray tracing and rasterizer architecture for mobile GPU

We present a bandwidth- and energy-efficient, hybrid ray tracing and rasterizer architecture for tile-based mobile GPU. In order to successfully commercialize mobile System on Chip (SoC), including ray tracing hardware solution, effective integration with rasterizer based on OpenGL---ES is indispensable for the performance and compatibility reason. Thus, recently, the traditional rasterizer-ray tracing hybrid approach is revisited to achieve this goal. The key factor for hybrid rendering is to reflect the fundamental principle of tile-based rendering on integrating the ray tracing hardware and mobile GPUs. Consequently, we propose a new architecture for hybrid rendering by combining new three features such as extended tile binning unit, tile prefetch, and per-tile power control. Simulation results show that our architecture is a potentially versatile solution for future mobile GPUs in low-energy devices because it provides as much as 31.7% better G-buffer bandwidth utilization and is up to 2.18 times better performance per unit energy compared to the ray tracing hardware-only solution.

Shading language compiler implementation for mobile ray tracing accelerator

This paper presents a shading language compiler optimized for a mobile ray tracing acclerator, i.e., SGRT (Samsung GPU Ray Tracing). By the compiler, application development productivity has been dramatically improved: 1) as an application-specific abstraction layer, a shading language makes it possible for application developers to implement ray generators and shaders much more easily and intuitively than with a general and low-level language, i.e., standard C language (up to 81.6% less source lines). 2) high performance is achievable without a deep understanding of the programmable shader architecture based on CGRA (Coarse-Grained Reconfigurable Array) which is complex to optimize especially in presence of many conditional branches (up to 1.58 times higher throughput).

PerfEPI: Parallel performance estimation with effective progress index

Multi-core system has merits in terms of energy efficiency and performance enhancement compared to the single core. However, design and development of a system using the multiple processors are very difficult, and in particular, verification of a system having concurrency may be difficult. This makes parallel system design hard, so developers must spend substantial amounts of time for design and debugging their programs. In this paper, we propose a novel design methodology with parallel performance estimator.

Adaptive multi-rate ray sampling on mobile ray tracing GPU

We present an adaptive multi-rate ray sampling algorithm targeting mobile ray-tracing GPUs. We efficiently combine two existing algorithms, adaptive supersampling and undersampling, into a single framework targeting ray-tracing GPUs and extend it to a new multi-rate sampling scheme by utilizing tile-based rendering and frame-to-frame coherency. The experimental results show that our implementation is a versatile solution for future ray-tracing GPUs as it provides up to 2.98 times better efficiency in terms of performance per Watt by reducing the number of rays to be fed into the dedicated hardware and minimizing the memory operations.

Latency tolerance techniques for real-time ray tracing on mobile computing platform

In this paper, we propose an efficient ray scheduling algorithm and non-block cache architecture to hiding main-memory access latency targeting real-time ray tracing on mobile device. We first analyze on the impact of a memory latency by analyzing the memory access patterns for a ray tracing system and present a novel ray scheduling method using a non-block pipeline feedback and cache architecture for ray tracing hardware engine. To achieve more cache efficiency, we also present a memory-efficient encoding scheme for the scene geometry. For an evaluation of our approach, we implemented a prototype ray tracing architecture using our approach on an FPGA platform. Our experimental results indicate that our approach shows that an average performance conservation of 85% and an average performance improves of 2.4 times.

Efficient high throughput rate cross-correlation logic design for sign-bit reference waveforms

This paper presents an efficient design method for high throughput rate cross-correlation logic using sign-bit reference waveforms which is one of widely equipped signal processing units in embedded consumer electronic devices. The proposed method minimizes resource usages by efficiently sharing the first level adders in adder trees of parallel sub-logics.