JeoungChill Shim

New non-volatile memory with extremely high density metal nano-dots

A new non-volatile memory with extremely high density metal nano-dots, MND (metal nano-dot) memory, was proposed and fundamental characteristics of the MND memory were evaluated. The MND film is used as a charge retention layer in the MND memory. The MND film consists of a thin oxide film that dispersively includes high density metal dots with nano-scale. The MND film is formed by using sputtering technique with a special sputtering target. The size and the density of the MND in the film are typically 2-3 nm and around 2/spl times/10/sup 13//cm/sup 2/, respectively, which were superior to that of Si quantum dot memory. Non-volatile memory operation at a relatively low voltage and good endurance characteristic were confirmed in the MND memory fabricated according to the conventional MOS process.

Proposal of New Nonvolatile Memory with Magnetic Nano-Dots

In this study, a new nonvolatile memory with magnetic nano-dots (MNDs) was proposed. A relatively large anisotropic change of gate current–voltage characteristics by the magnetization in magnetic non-volatile memory with Co nano floating gate and Ni-Fe control gate was obtained. A Co magnetic nano-dot film with very high dot density of 2×1013 cm-2 was successfully formed by sputtering with optimized target composition. A small anisotropic change of gate current–voltage characteristics by the magnetization in MND memory with Co MNDs and Ni-Fe control gate was observed.

Novel Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors with Buried Back Gate

One of the most promising ways of realizing metal oxide semiconductor field effect transistors (MOSFETs) with high speed and ultralow power consumption is by varying the threshold voltage of fully depleted silicon on insulator (FD-SOI) MOSFETs by changing back gate bias. We have studied FD-SOI MOSFETs with buried back gate by experiment and simulation in order to realize both high-performance and low-voltage ULSIs. It was confirmed that the back gate is very effective not only for increasing the ON current in the active mode but also for decreasing the cut-off current in the standby mode by controlling the threshold voltage.

Proposal of New Non-Volatile Memory with Magnetic Nano-Dots

We proposed a new non-volatile memory with magnetic nano-dots (MND) dispersed in an insulating film as charge retention layer. We evaluated fundamental characteristics of FePt magnetic nano-dot film which is employed in such new magnetic nano-dot memory. We successfully formed a highly ordered L1 0 phase face-centered tetragonal structured FePt nano-dot ( < 4.2nm) films on Si 3 N 4 (5nm)/SiO 2 (10nm)/silicon substrates and SiO 2 (10nm)/ silicon substrate by using SAND method. The uniformity of FePt particle size is dramatically improved by introducing a Si 3 N 4 buffer layer on SiO 2 /Si substrate. In addition, it is found that FePt nano-dot film formed on Si3N4(5nm)/Si02(10nm)/Si substrate has a large coerce-ivity of ∼22 kOe at room temperature.

Design and evaluation of a novel real-shared cache module for high performance parallel processor chip

Nowadays, it is very important that integrating parallel processors on a chip offers high performance and low interactive response time on applications with fine-grained parallelism and high degree of data sharing. We propose a novel real-shared cache module with new multiport ring-bus architecture to overcome the bus bottleneck problem of the existing parallel processors chip on shared cache level. A testbench of solving a large scale of simultaneous linear equation is also designed to evaluate such architecture. The evaluation results show that it can offer immediate data sharing without conflicts or delay, and the performance of parallel processors chips with such novel real-shared cache module improves in proportion to the number of processor elements.

SOI NMOSFETs with SiGe elevated S/D and Ni silicide

SiGe selective epitaxial growth(SEG) and Ni silicidation technologies were developed for realizing high performance SOI MOSFETs with high current drivability. Then these technologies were applied for SOI MOSFET with elevated source/drain structure. The source/drain with the sheet resistance of 7/spl Omega//square could be obtained.