Hiroyuki Kurino

Future system-on-silicon LSI chips

A new three-dimensional (3D) integration technology to achieve system-on-silicon LSIs has been proposed. Several LSI wafers are vertically stacked and glued each other after thinning them in this 3...The development of system-on-silicon large-scale integration (LSI) devices has significantly influenced the demand for higher wiring connectivity within LSI chips. Currently, increasing the number of metal layers in a multilevel metallization as the device size decreases increases wiring connectivity. In the future, however, designers will have difficulty catching up with the rising demand for higher wiring connectivity by merely increasing the number of metal layers. We propose a new three-dimensional integration technology to overcome future wiring connectivity crises. In our solution, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using our new integration technology. More than 10/sup 5/ interconnections per chip form in a vertical direction in these 3D LSI chips or 3D MCMs. Consequently, we can dramatically increase wiring connectivity while reducing the number of long interconnections.

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip

Three-dimensional shared memory fabricated using wafer stacking technology

We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

Intelligent image sensor chip with three dimensional structure

A new three-dimensional (3D) integration technology based on wafer bonding technique has been proposed for intelligent image sensor chip with 3D stacked structure. We have developed key technologies for such 3D integration. A 3D image sensor test chip was fabricated using this 3D integration technology. Basic electric characteristics were evaluated in the 3D image sensor test chip.

Neuromorphic vision chip fabricated using three-dimensional integration technology

Information processing in the human brain is based on advanced parallel processing with a large number of memories and interconnections. To achieve such highly advanced parallel processing, the human brain has modules with layered structures, that is, three-dimensional structures as basic processing units. The human retina and visual cortex also have layered structures with various kinds of cells. The three-dimensional (3D) integration technology reported here achieves an image processing and pattern recognition system with parts of functions of the retina and visual cortex using silicon.

New non-volatile memory with extremely high density metal nano-dots

A new non-volatile memory with extremely high density metal nano-dots, MND (metal nano-dot) memory, was proposed and fundamental characteristics of the MND memory were evaluated. The MND film is used as a charge retention layer in the MND memory. The MND film consists of a thin oxide film that dispersively includes high density metal dots with nano-scale. The MND film is formed by using sputtering technique with a special sputtering target. The size and the density of the MND in the film are typically 2-3 nm and around 2/spl times/10/sup 13//cm/sup 2/, respectively, which were superior to that of Si quantum dot memory. Non-volatile memory operation at a relatively low voltage and good endurance characteristic were confirmed in the MND memory fabricated according to the conventional MOS process.

New Three-Dimensional Wafer Bonding Technology Using the Adhesive Injection Method

A new three-dimensional (3D) wafer bonding technology using the adhesive injection method has been proposed, in order to realize a real-time micro-vision system and a real shared memory. Several key technologies for 3D LSI, such as deep trench formation for buried interconnection, wafer grinding and chemical-mechanical polishing, wafer alignment and wafer bonding using the adhesive injection method, have been developed.

Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip

A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.

A New Wafer Scale Chip-on-Chip (W-COC) Packaging Technology Using Adhesive Injection Method

In order to realize low cost and high density packaging technology, we propose a new wafer scale chip-on-chip (W-COC) packaging technology using the adhesive injection method. In W-COC packaging technology, chip-on-chip modules more than two hundreds are simultaneously formed at the wafer level. In addition, we can significantly improve the chip performance, because small micro-bumps, more than one million, can be formed on a chip and consequently a number of vertical interconnections can be formed between the two bonded chips. Therefore, it is very easy to introduce the parallel processing function in a W-COC module. Using this technology, we propose a new multichip module (MCM) consisting of single or multiple memory chips directly attached to a logic chip. In this paper, we describe key technologies to realize this new multichip module. We fabricated the W-COC test module and investigated its electrical performance using a micro-bump chain.

Three-Dimensionally Stacked Analog Retinal Prosthesis Chip

As blind patients with an intact optic nerve and damaged photoreceptor cells increase in number in recent years, there has been a growing interest in visual prostheses by electrically stimulating their retinas. Previous clinical studies indicated that blind patients perceive a controlled electrical current applied to a small area of the retina via electrodes as a spot of light. We propose a novel implantable device, so-called three-dimensionally (3D) stacked retinal prosthesis, which is composed of a photodetector, an image processor, electrical current generator circuits, and an electrode array on one chip. The spice simulation showed that our designed analog circuits for 3D stacked retinal prosthesis chip could output desirable electrical current with variable pulse width by controlling bias voltages.