Jeremy C. Smith

A fault-tolerant CEQRNS processing element for linear systolic array DSP applications

The design of a Galois enhanced quadratic residue number system (GEQRNS) processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been optimized to perform multiply-accumulate type operations on complex operands. The properties of finite fields have been exploited to perform this complex multiplication in a manner which results in greatly reduced hardware complexity. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which can occur during operation. The combination of these two factors makes this an ideal candidate for array signal processing applications, where high complex arithmetic data rates are required. A prototype processing element has been fabricated in 1.5 /spl mu/m CMOS technology, which is shown to operate at 40 MHz. >

An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOS/ESD events

In this work, an anti-snapback circuit technique called source injection (SI) is presented for the first time, which is shown to inhibit parasitic bipolar conduction during EOS/ESD events. The design is presented for a fully salicided, 0.25 /spl mu/m, 35 /spl Aring//70 /spl Aring/ dual gate oxide, thin-epi, retrograde n-well, bulk CMOS technology. The technique is shown to greatly extend the snapback voltage of NMOS devices in this technology, which are usually destroyed instantaneously once snapback occurs. The design also has the benefit of controlling output buffer impedances for impedance matching to transmission-line loads. The design is fully compatible with the baseline process and has been shown to increase ESD robustness for positive discharge stress modes, which are the most difficult to protect for in epi processes. An increase of >1.5 kV is demonstrated for HBM, an increase of 550 V is shown for MM, and an increase of >550 V is exhibited for CDM, over nonSI and SI I/O pad designs, respectively.

ESD protection in thin film silicon on insulator technologies

This paper reviews some of the devices and circuits which have been used to implement ESD protection networks for thin film silicon on insulator (TFSOI) technologies. The high current behavior of TFSOI MOSFETS and diodes is described for both positive and negative discharges. Next, several representative pin-protection network designs are reviewed which have all been shown to provide industry-standard levels of ESD protection. A discussion of power-supply protection networks follows, which must be used in conjunction with the pin protection schemes.

CMOS TSPC latch circuits for pass-transistor logic

In this work, latch circuits are presented for the design of true single phase clocked (TSPC) pass-transistor (PT) networks. The latches consist of N-clocked and P-clocked sections, which can be used in conjunction with NMOS pass-transistor networks to implement general logic functions. In each N or P section, the signal to be latched is input to a positive feedback regenerative circuit, which restores the incomplete logic-level at the output of the latch. The latch sections rely on the circuit topology to minimize power dissipation resulting from reduced input signal swing, rather than on transistor threshold adjustments or special well or substrate biasing. Thus, it is possible to realize pass-transistor circuits with reduced power dissipation in ordinary CMOS processes.