Percy V. Gilbert

Practical applications of 2-D optical proximity corrections for enhanced performance of 0.25 /spl mu/m random logic devices

Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of-the-art 0.25 /spl mu/m random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.

A high performance 1.5 V, 0.10 /spl mu/m gate length CMOS technology with scaled copper metallization

A high performance 0.10 /spl mu/m gate length CMOS technology has been developed with six levels of scaled copper interconnects. Transistors of 0.10 /spl mu/m-0.13 /spl mu/m gate length with physical 3 nm gate oxides and 0.175 /spl mu/m local interconnect features are optimized for 1.5 V operation to achieve 15 ps unloaded ring oscillator delay. Complementary phase shift masks for superior gate control and low-K dielectrics for reduced coupling capacitance enable an aggressive (>15%) linear shrink of the previous generation copper-based technology. Critical technology layer pitches enable fabrication of 4.5 /spl mu/m/sup 2/ 6T-SRAM cells.

Optimization of a 0.18 /spl mu/m 1.5 V CMOS technology to achieve 15 ps gate delay

Summary form only given. A high performance 0.18 /spl mu/m CMOS technology with minimum 0.1 and nominal 0.13 /spl mu/m poly gate, physical 3 nm gate oxide, and 0.18 /spl mu/m local interconnect features operating at 1.5 V supply voltage is described with emphasis on the reduction of parasitic capacitances and resistances while maintaining high drive currents and low leakage currents to achieve a 15 ps unloaded ring oscillator delay. Coupling capacitance between gate and local interconnect is also discussed as a function of technology scaling as is 3 nm gate oxide reliability.

Latch-up performance of a sub-0.5 micron inter-well deep trench technology

The latch-up performance of a 3.3 volt, sub-0.5 micron, non-epitaxial bulk CMOS technology is described. For the first time, we present measured data which shows the holding voltage of the inter-well deep trench structure increases with reduced N/sup +P/sup +/ spacing. All other technologies, including the thin epi on P/sup +/ substrate process, suffer a decrease in holding voltage as the N/sup +P/sup +/ spacing is reduced. PISCES 2D simulations illustrate that the increase in holding voltage for the inter-well deep trench structure is due to enhanced current confinement along the trench sidewall. For the PNPN test device with an N/sup +P/sup +/ spacing of 2 /spl mu/m, the holding voltage is as high as 4.8 volts for the inter-well deep trench structure as compared to 1.5 volts for the bulk CMOS structure. The inter-well deep trench technology provides a 10/spl times/ improvement in holding current (60 mA) as compared to non-trench, bulk CMOS (6 mA). The fabricated inter-well deep trench structure also demonstrates excellent immunity to sidewall inversion, with sidewall leakage current less than 0.08 pAspl mu/m.<<ETX>>

A 0.25 /spl mu/m CMOS technology with 45 /spl Aring/ NO-nitrided oxide

This paper describes the device design and fabrication of a 0.25 /spl mu/m CMOS process integrated with 45 /spl Aring/ oxynitride gate dielectric for high-performance logic applications. Channel profile engineering is applied to control short-channel effects. With TiN-capped Co salicide, the gate sheet resistance is reduced to less than 5 /spl Omega//sq at 0.18 /spl mu/m. Ring oscillator gate delay of 26 ps/stage is accomplished at a supply voltage of 1.8 V.

0.25-μm logic manufacturability using practical 2D optical proximity correction

Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data improvements in reticle manufacturability, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.

A manufacturable and modular 0.25 /spl mu/m CMOS platform technology

A modular 0.25 /spl mu/m CMOS core technology suitable for high density and high-performance or low-power applications is presented. The key salient features include: simple 1-mask STI, 40 /spl Aring/ high-performance or low-power CMOS transistor modules, cobalt salicide, a practical 2D Optical Proximity Correction (OPC) technique applied to tight-pitch local interconnect and 6-level tiled metallization backend that include unlanded vias and no-cap Inter-Level Dielectric (ILD). This technology is capable of producing state-of-the-art 380 MHz RISC microprocessors (47 mm/sup 2/) with 9.4 /spl mu/m/sup 2/ 6 T bitcell SRAM. The modularity of the process architecture allows the subsequent expansion of the integration to a wide-range of applications.

A PELOX isolated sub-0.5 micron thin-film SOI technology

The integration of Poly-Encapsulated LOCOS (PELOX) into a high performance sub-0.5 /spl mu/m thin-film SOI technology is described. The 700 /spl Aring/ (per side) birds beak encroachment of PELOX eliminates the need for a field implant and results in a significant reduction of the MOSFET narrow width effect. Partially-depleted N+/P+ dual poly gate MOSFETs with 70 /spl Aring/ Tox and 0.35 /spl mu/m Lpoly were fabricated with /spl les/1 /spl mu/m active/isolation pitch. A 40% reduction in power-delay product, compared to bulk CMOS, is achieved with a CMOS ring oscillator propagation-delay of 51 psec at 2 V supply voltage.

Impact of photoresist taper and implant tilt angle on the interwell isolation of subquarter-micron CMOS technologies

The impact of photoresist taper and implant tilt angle on the interwell isolation of a sub-0.25 micrometer CMOS technology is investigated. It is shown that as the trench depth is decreased and the n-well dose and energy is increased, interwell isolation below 1 micron N+/P+ spacing is degraded. The reduction of photoresist taper is shown to be a key factor in improving interwell isolation and decreasing MOSFET device parasitics. By optimizing the photoresist process to minimize taper, acceptable N+/P+ isolation is achieved down to 0.7 micrometers. Also, by utilizing a two dimensional interwell isolation test structure, it is found for the first time that as the interwell isolation is scaled into the sub-micron regime, lateral n-well dopant displacement caused by the implant tilt angle can result in reduced overlay margin.

Performance improvement of a thick field oxide ESD protection circuit by halo implant

Optimization of a sub-0.5 /spl mu/m ESD protection circuit using halo implant is described. A p-type halo implant significantly improves the ESD robustness of a high performance I/O circuit as noted by Human Body Model (HBM) test results. The improved ESD performance is directly attributed to the ability of the halo implanted Thick Field Oxide (TFO) device to inhibit the turn-on of the n-channel output buffer during an ESD event. Improved ESD performance is achieved without the use of additional series resistance and with no increase in device area. The results represent the first time transmission-line pulse generator (TLPG) analysis has been used on a fully synthesized I/O circuit to predict wafer level ESD performance.