Jeremy Holleman

A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations

A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 0.13 mum CMOS process. The circuit consumes 162 nW from a 1 V supply at low readout frequencies and 1.6 muW at 1 Mb/s. Cross-coupled logic gates were employed to simultaneously generate, amplify, and digitize the random circuit offset to create a stable unique digital chip ID code. A thorough statistical analysis is presented in order to explore the ID circuit reliability and stability. Two ID generators with different layout techniques were designed and fabricated to provide a performance comparison of power consumption, ID stability, and ID statistical robustness.

A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations

A 128b 6.3pJ/b, 96%-stable chip-ID generation circuit using process variation is designed in a 0.13mum CMOS technology. The circuit consumes 162nW from a 1V supply at low readout frequencies and 6.34muW at 1 Mb/s. Two layout techniques are designed and fabricated to provide a performance comparison of power consumption and ID reliability

Design of Ultra-Low Power Biopotential Amplifiers for Biosignal Acquisition Applications

Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large number of front-end amplifiers in multichannel implantable systems, the power consumption of each amplifier must be minimized. This paper introduces a closed-loop complementary-input amplifier, which has a bandwidth of 0.05 Hz to 10.5 kHz, an input-referred noise of 2.2 μ Vrms, and a power dissipation of 12 μW. As a point of comparison, a standard telescopic-cascode closed-loop amplifier with a 0.4 Hz to 8.5 kHz bandwidth, input-referred noise of 3.2 μ Vrms, and power dissipation of 12.5 μW is presented. Also for comparison, we show results from an open-loop complementary-input amplifier that exhibits an input-referred noise of 3.6 μ Vrms while consuming 800 nW of power. The two closed-loop amplifiers are fabricated in a 0.13 μ m CMOS process. The open-loop amplifier is fabricated in a 0.5 μm SOI-BiCMOS process. All three amplifiers operate with a 1 V supply.

A Sub-Microwatt Low-Noise Amplifier for Neural Recording

In this paper we present a pre-amplifier designed for neural recording applications. Extremely low power dissipation is achieved by operating in an open-loop configuration, restricting the circuit to a single current branch, and reusing current to improve noise performance. Our amplifier exhibits 3.5 microVrms of input-referred noise and has a digitally-controlled gain between 36dB and 44dB. The amplifier is AC-coupled, with a pass-band from 0.3 Hz to 4.7kHz. The circuit is implemented in a 0.5 microm SOI Bi-CMOS process and consumes 805nA from a 1.0V supply, corresponding to a noise efficiency factor (NEF) of 1.8, which is the lowest reported NEF to date.

NeuralWISP: A Wirelessly Powered Neural Interface With 1-m Range

We present the NeuralWISP, a wireless neural interface operating from far-field radio-frequency RF energy. The NeuralWISP is compatible with commercial RF identification readers and operates at a range up to 1 m. It includes a custom low-noise, low-power amplifier integrated circuit for processing the neural signal and an analog spike detection circuit for reducing digital computational requirements and communications bandwidth. Our system monitors the neural signal and periodically transmits the spike density in a user-programmable time window. The entire system draws an average 20 muA from the harvested 1.8-V supply.

A 500µW neural tag with 2µV rms AFE and frequency-multiplying MICS/ISM FSK transmitter

Advances in electronic-neural interfaces have shown great potential for both neuroscience research and medical devices. Much of the work to date has focused on short-range inductive links for power and communication transfer [1]. There is an emerging need for active miniaturized systems that stream neural data in the far field, which would enable the observation of brain activity in unconstrained animals such as mice or moths. Such systems cannot rely on near-field power transfer, and must be powered by small batteries or energy harvesters. We present a 500µW fully integrated neural interface that wirelessly streams a digitized neural waveform over 15m.

A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation

A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay. The design has been fabricated in a commercially available 0.5-μm process. Measurement results of 10 circuits show a reduction of offset standard deviation from 5.415 mV to 50.57 μV, improved by a factor of 107.1. The offset cancellation scheme does not introduce observable offset or noise, and can achieve fast and robust convergence with a wide range of common mode input. Operating at a supply of 5 V and clock frequency of 200 kHz, the comparator together with the OC circuitry consumes 4.65 μW of power, or 23 pJ of energy per comparison.

30.10 A 1TOPS/W analog deep machine-learning engine with floating-gate storage in 0.13μm CMOS

An analog implementation of a deep machine-learning system for efficient feature extraction is presented in this work. It features online unsupervised trainability and non-volatile floating-gate analog storage. It utilizes a massively parallel reconfigurable current-mode analog architecture to realize efficient computation, and leverages algorithm-level feedback to provide robustness to circuit imperfections in analog signal processing. A 3-layer, 7-node analog deep machine-learning engine was fabricated in a 0.13 μm standard CMOS process, occupying 0.36 mm 2 active area. At a processing speed of 8300 input vectors per second, it consumes 11.4 μW from the 3 V supply, achieving 1×10 12 operation per second per Watt of peak energy efficiency. Measurement demonstrates real-time cluster analysis, and feature extraction for pattern recognition with 8-fold dimension reduction with an accuracy comparable to the floating-point software simulation baseline.

NeuralWISP: An energy-harvesting wireless neural interface with 1-m range

We present the NeuralWISP, a wireless neural interface operating from harvested RF energy. The NeuralWISP is compatible with commercial RFID readers and operates at a range up to 1m. It includes a custom low-noise, low power amplifier IC for processing the neural signal and an analog spike detection circuit for reducing digital computational requirements and communications bandwidth. Our system monitors the neural signal and periodically transmits the spike density in a user-programmable time window. The entire system draws an average 20 muA from the harvested 1.8V supply.

A 3

This paper presents two novel hardware random number generators (RNGs) based on latch metastability. We designed the first, the DC-nulling RNG, for extremely low power operation. The second, the FIR-based RNG, uses a predictive whitening filter to remove nonrandom components from the generated bit sequence. In both designs, the use of floating-gate memory cells allows us to predict and compensate for DC offsets and other nonrandom influences while minimizing power consumption. We also present an efficient digital post-processing technique for improving randomness. We fabricated both RNGs in a standard 0.35 mum CMOS process. The DC-nulling RNG occupied .031 mm2 of die area, while the FIR-based RNG occupied 1.49 mm2.