Seth Bridges

A 3

This paper presents two novel hardware random number generators (RNGs) based on latch metastability. We designed the first, the DC-nulling RNG, for extremely low power operation. The second, the FIR-based RNG, uses a predictive whitening filter to remove nonrandom components from the generated bit sequence. In both designs, the use of floating-gate memory cells allows us to predict and compensate for DC offsets and other nonrandom influences while minimizing power consumption. We also present an efficient digital post-processing technique for improving randomness. We fabricated both RNGs in a standard 0.35 mum CMOS process. The DC-nulling RNG occupied .031 mm2 of die area, while the FIR-based RNG occupied 1.49 mm2.

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This paper presents two novel hardware random number generators (RNGs) based on latch metastability. We designed the first, the DC-nulling RNG, for extremely low power operation. The second, the FIR-based RNG, uses a predictive whitening filter to remove non-random components from the generated bit sequence. In both designs, the use of floating-gate memory cells allows us to predict and compensate for DC offsets and other non-random influences while minimizing power consumption. We also present a simple post-processing technique for improving randomness. We fabricated both RNGs in a standard 2P4M 0.35 μm CMOS process. The DC-nulling RNG utilized .031 mm2 of die area, while the FIR-based RNG occupied 1.49 mm2.

W CMOS True Random Number Generator With Adaptive Floating-Gate Offset Cancellation

We have built a 48-tap, mixed-signal adaptive FIR filter with 8-bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the least mean square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed-signal multipliers, and adapt the tap coefficients using pulse-based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in a 0.35-/spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200 MHz, and consumes 20 mW providing a 6-mA differential output current.

A 2.92μW Hardware Random Number Generator

We present a reconfigurable array for low-power feedforward neural networks in analog VLSI. This architecture implements a flexible computational model with coarse-grained reconfigurability, and features high computational density for a broad range of applications. Our prototype of the array, fabricated in a 0.35/spl mu/m process, consumes 0.25mm/sup 2/ of area and dissipates 150/spl mu/W of power on a 5V supply. In this paper, we discuss the circuits and architecture of our system, as well as experimental results.

A 19.2 GOPS mixed-signal filter with floating-gate adaptation

We describe analog and mixed-signal primitives for implementing adaptive signal-processing algorithms in VLSI based on anti-Hebbian learning. Both on-chip calibration techniques and the adaptive nature of the algorithms allow us to compensate for the effects of device mismatch. We use our primitives to implement a linear filter trained with the least-mean squares (LMS) algorithm and an adaptive decorrelation network that improves the convergence of LMS. When applied to an adaptive code-division multiple-access (CDMA) despreading application, our system, without the need for power control, achieves more than 100× improvement in the bit-error ratio in the presence of high interference between users. Our 64-tap linear filter uses 0.25mm2 of die area and dissipates 200μW in a 0.35μm CMOS process.

A reconfigurable VLSI learning array

Device mismatch, charge leakage and nonlinear transfer functions limit the resolution of analog-VLSI arithmetic circuits and degrade the performance of neural networks and adaptive filters built with this technology. We present an analysis of the impact of these issues on the convergence time and residual error of a linear perceptron using the Least-Mean-Square (LMS) algorithm. We also identify design tradeoffs and derive guidelines to optimize system performance while minimizing circuit die area and power dissipation.

Adaptive signal processing in mixed-signal VLSI with anti-Hebbian learning

This paper introduces adaptive delay sequential elements (ADSEs). ADSEs are registers that use nonvolatile, floating-gate transistors to tune their internal clock delays. We propose ADSEs for correcting timing violations and optimizing circuit performance. We present an ADSE circuit example, system architecture, and tuning methodology. We present experimental results that demonstrate the correct operation of our example circuit and discuss the die-area impact of using ADSEs. Our experiments also show that voltage and temperature sensitivity of ADSEs are comparable to non-adaptive flip-flops.

Effects of Analog-VLSI hardware on the performance of the LMS algorithm

In this paper, we present a novel CMOS imager architecture that implements the random projection dimensionality reduction algorithm in the focal plane. We employ analog signal processing techniques to achieve low-power operation and our imager can readily integrate with known low-power VLSI classifiers. We fabricated a 20 times 20 pixel prototype of our 4.2mm2 imager in 0.35 mum CMOS that performs 1GOPS while consuming 1.25mW of power from a 5V supply

Timing correction and optimization with adaptive delay sequential elements

We implemented a 48-tap, mixed signal adaptive FIR filter with 8-bit input and 10-bit output resolution. The filter stores its tap weights in nonvolatile analog memory cells and adapts using the least-mean-square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed-signal multipliers, and adapt the tap coefficients using pulsed-based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in an 0.35/spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200MHz, and consumes 20mW providing a 6mA differential output current.