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Featured researches published by Jesus Guinea.


IEEE Transactions on Very Large Scale Integration Systems | 2005

A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability

Francesco Centurelli; Alessandro Golfarelli; Jesus Guinea; Leonardo Masini; Damiana Morigi; Massimo Pozzoni; Giuseppe Scotti; Alessandro Trifiletti

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies


radio frequency integrated circuits symposium | 2003

A 10 Gb/s CDR in SiGe BiCMOS commercial technology with multistandard capability

Francesco Centurelli; Alessandro Golfarelli; Jesus Guinea; Leonardo Masini; Damiana Morigi; Massimo Pozzoni; Giuseppe Scotti; Alessandro Trifiletti

A 10 Gb/s CDR in SiGe BiCMOS technology featuring multistandard compliance with SDH/SONET and 10 Gb Ethernet specs and generated jitter below 65 mUlpp is presented. The CDR features a 20 mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize CPM and a dual loop PLL architecture with external reference clock and a novel PD topology. Power consumption is below 780 mW from 2.5 and 3.3 V supplies.


european solid-state circuits conference | 2012

An instrumentation 128dB-SNR 750μA SDM

Jesus Guinea; Enrico Sentieri; A. Baschirotto

One of the largest SDM DR is achieved at low power consumption by means of several SC design solutions, like multi-bit topology, large OSR, improved switching scheme, chopper & NMOS input pair, accurate opamp design. In a 3.3V 0.35μm CMOS technology, 128dB-DR in a 250Hz bandwidth is achieved with 0.75mA current from a single 2.4mW supply for high-performance instrumentation application.


Annales Des Télécommunications | 1993

Vlsi solutions for voice and channel coders

Pietro Erratico; Germano Nicollini; Jesus Guinea; Fran·ois Druilhe; Serge Ramet; Thierry Fensch

In the last few years we have seen a relevant transformation of the telephone network, with an extensive digitalization of the voice transmission and switching able now to reach the subscriber. In the meanwhile various techniques have been implemented to exploit data transmission in an environment designed for voice only. This paper will review this important transformation and its future perspective from the point of view of theic industry by considering several analog/digital basic realization inpcm, analog modem,isdn and radio-communication fields.RésuméLes dernières années ont été caractérisées par une transformation significative des réseaux téléphoniques, avec numérisation de plus en plus grande de la transmission et de la commutation jusqu’ à ľabonné lui-même. En même temps, des techniques variées ont été mises en place pour exploiter la transmission de données dans un environnement jusqu’ici conçu pour la voix. Ľarticle prend en compte cette transformation et ses conséquences futures dans le domaine de ľIndustrie microélectronique, en s’appuyant sur plusieurs réalisations concrètes de circuits analogiques et numériques dans le domaine dumic (codec à capacités commutées, joncteur ďabonné à processeur de signal), des modems analogiques, durnis (numérisation de la ligne ďabonné) et des radiocommunications avec les mobiles (traitement du signal vocal en bande de base).


Archive | 2001

Synchronism phase-switching circuit for the recovery of received data

Jesus Guinea; Massimiliano Rutar; Luciano Tomasini


Archive | 2000

Bidirectional synchronous interface with single time base

Jesus Guinea; Luciano Tomasini


Archive | 2003

Input stage for a buffer with negative feed-back

Luciano Tomasini; Jesus Guinea


Archive | 2002

Delay locked loop circuit with convergence correction

Jesus Guinea; Luciano Tomasini


Archive | 2001

Improved delay locked loop circuit

Jesus Guinea; Luciano Tomasini


Archive | 2001

Circuit system suitable for codifying NRZ type binary signals into CMI type binary signals

Jesus Guinea; Carlo Maria Milanese

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Giuseppe Scotti

Sapienza University of Rome

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