Jesús María Vegas Hernández

Design of a current-mode continuous-time Sigma-Delta modulator with exponential feedback for improved jitter rejection

In this article a current-mode, second-order, CT Sigma-Delta modulator operating at a sampling frequency of 25 MHz and with an oversampling ratio of 64 has been designed. The modulator consists of current-mode, differential integrators based on a single-stage folded cascode topology and switched capacitors DACs cells generating exponential feedback waveforms. The modulator was analysed in detail from both a system- and a circuit-level point of view. A ‘short’ exponential DAC pulse, namely, an exponential pulse whose time constant is lower than the pulse width, was used to improve jitter rejection. Modulator feedback coefficients were analytically derived for an exponential feedback waveform. Jitter considerations paying special attention to its impact on CT Sigma-Delta modulators were presented, and two different contributions distinguished: independent jitter and accumulated jitter. Finally, functional- and transistor-level simulations have been accomplished to obtain significant features of the modulator performance.

A 1.2V, 130nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers

The design and implementation in a 1.2V, 130nm CMOS technology of a parallel continuous-time @S@D modulator for OFDM UWB signals is described. Once the parallel architecture and the metrics used are presented, the NTF is optimized and implemented using a third order lowpass and a fourth order bandpass modulator. Both are CRFB structures which use active-RC integrators. Then, the circuital blocks are discussed and some comments about the test set-up are given. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15dB DR for QPSK modulation over a signal bandwidth of 528MHz, with a 62.3mW power consumption.

Design of a 1-V 1-MS/s Track&Hold circuit based on the switched opamp approach

A very low voltage solution for the realization of the hold capacitor in a Track&Hold circuit based on an open-loop architecture is introduced. The circuit is a modification based on the switched opamp approach of the Track&Hold circuit using Miller Capacitance. Simulations show that the circuit is able to operate at 1V 1MS/s with a Total Harmonic Distortion of −64 dB @ 100 kHz and a very low power consumption of 80 µW.

LC-based clock generator for high-frequency, continuous-time, ΔΣ ADCs

This paper presents the design and experimental results of a clock generator for high-frequency, continuous-time, converters. The circuit was fabricated in a -V, -nm CMOS technology along with two modulators intended for the digitisation of UWB signals. The clock generator is based on a PLL frequency synthesiser with a low phase noise LC Voltage-controlled oscillatror (VCO). This kind of oscillator achieves the required low jitter specification with a substantial lower power consumption than a conventional ring VCO. In order to save die area, the VCO was made to operate at four times the desired clock frequency of MHz, and a compact multi-layer inductor was used. A system clock with a cycle-to-cycle jitter of only of its period is obtained. The total circuit area is and the resulting power consumption is .

A parallel, CT-ΔΣ based ADC for OFDM UWB receivers in 130 nm CMOS

The design and implementation in a 1.2 V, 130 nm CMOS technology of an ADC intended for OFDM UWB signals is described. This ADC is based on parallel, continuous-time ΣΔ modulators, and employs an OFDM-optimized NTF, implemented using a 3rd order lowpass and a 4t order bandpass modulator. Both are CRFB structures which use active-RC integrators. “Early DAC” clocking is used to reduce the GBW of opamps. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15 dB DR for QPSK modulation.

The Role of Incomplete Interstitial-Vacancy Recombination on Silicon Amorphization

We investigate the role that point defects and interstitial-vacancy pairs have on the Si amorphization process using molecular dynamics techniques. We show that accumulation of interstitial-vacancy pairs in concentrations of 25% and above lead to homogeneous amorphization. We identify very stable defect structures, consisting of the combination of the pair and Si self-interstitials, which form when there is an excess of interstitials or by incomplete interstitial-vacancy recombination in a highly damaged lattice. These defects could survive long enough at room temperature to act as embryos for the formation of extended amorphous zones and/or point defect clusters.