Jokin Segundo

Parallel Continuous-Time

A parallel multibit continuous-time (CT) DeltaSigma analog-to-digital converter for an orthogonal-frequency-division-multiplexing (OFDM) ultrawideband receiver intended to operate according to the IEEE 802.15.3a or the ECMA 368 (ISO/IEC 26907) standards has been designed. The overall CT DeltaSigma converter consists of two modulators covering two unequal subbands (low-pass (LP) and bandpass (BP) subbands) that are arranged to operate in parallel and whose respective noise transfer functions (NTFs) are designed to match its corresponding frequency band. The composite NTF for the overall converter is defined as the minimum gain value out of these two individual NTFs. The LP and BP subbands were designed by using third- and fourth-order modulators, respectively, based on a 3-bit quantizer and operating at a clock frequency of 1056 MHz. NTF zero locations were optimized according to the criterion that all the in-band composite NTF gain maxima have approximately the same value. Combining OFDM signal characteristics and converter parameters, the effect of the quantization noise on the overall converter performance has been analytically derived. A simulation program has been realized to verify the performance of the converter.

\Delta\Sigma

In this work the design of a continuous-time @D@S modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5MHz and 8, resulting in a clock frequency of 1GHz. It was designed and implemented in a standard 90nm CMOS technology. The active area of the modulator measures 0.0207mm^2. It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8mW from a nominal power supply of 1V.

ADC for OFDM UWB Receivers

A detailed analysis of the impact of a hysteretic quantizer on a multibit, Sigma-Delta modulator has been carried out in this paper. Both discrete-time and continuous-time modulators have been considered. A qualitative modeling of the hysteretic quantizer based on a hysteretic block followed by an ideal quantizer was proposed. Due to the hysteresis effect, the quantizer output signal is delayed and distorted with respect to the quantizer input signal, where the delay causes a phase-shift independent on the signal frequency. Yet, the effect of the hysteresis depends on the input signal amplitude. This model was validated by using system-level simulations for a second order, 3-bit, discrete-time Sigma-Delta modulator. A linear model for hysteresis was derived by assuming a narrow hysteresis cycle. The quantizer input signal plays a fundamental role in the discussion. In order to include this signal into the linear analysis some approximations are proposed. The quantizer output signal is decomposed by the use of the Fourier series analysis only into the in-phase and quadrature components (with respect to the input signal) whose Fourier series coefficients can be analytically calculated. A quantitative analysis for both a second order, 3-bit, DT and CT Sigma-Delta modulators including a hysteretic quantizer was carried out. For the CT modulator, finite GBW in amplifiers, excess loop delay, and a hysteretic quantizer were considered separately and combined. A good agreement with both system-level simulations and experimental results is found, despite the approximations considered for the quantizer input signal.

A 1-GHz, multibit, continuous-time, delta-sigma ADC for Gigabit Ethernet

In this article a current-mode, second-order, CT Sigma-Delta modulator operating at a sampling frequency of 25 MHz and with an oversampling ratio of 64 has been designed. The modulator consists of current-mode, differential integrators based on a single-stage folded cascode topology and switched capacitors DACs cells generating exponential feedback waveforms. The modulator was analysed in detail from both a system- and a circuit-level point of view. A ‘short’ exponential DAC pulse, namely, an exponential pulse whose time constant is lower than the pulse width, was used to improve jitter rejection. Modulator feedback coefficients were analytically derived for an exponential feedback waveform. Jitter considerations paying special attention to its impact on CT Sigma-Delta modulators were presented, and two different contributions distinguished: independent jitter and accumulated jitter. Finally, functional- and transistor-level simulations have been accomplished to obtain significant features of the modulator performance.

Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator

The design and implementation in a 1.2V, 130nm CMOS technology of a parallel continuous-time @S@D modulator for OFDM UWB signals is described. Once the parallel architecture and the metrics used are presented, the NTF is optimized and implemented using a third order lowpass and a fourth order bandpass modulator. Both are CRFB structures which use active-RC integrators. Then, the circuital blocks are discussed and some comments about the test set-up are given. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15dB DR for QPSK modulation over a signal bandwidth of 528MHz, with a 62.3mW power consumption.

Design of a current-mode continuous-time Sigma-Delta modulator with exponential feedback for improved jitter rejection

A very low voltage solution for the realization of the hold capacitor in a Track&Hold circuit based on an open-loop architecture is introduced. The circuit is a modification based on the switched opamp approach of the Track&Hold circuit using Miller Capacitance. Simulations show that the circuit is able to operate at 1V 1MS/s with a Total Harmonic Distortion of −64 dB @ 100 kHz and a very low power consumption of 80 µW.

A 1.2V, 130nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers

A comprehensive analysis of the impact of the finite gain-bandwidth product (GBW) in amplifiers and the excess loop delay on a parallel multibit CT ΔΣ ADC for an orthogonal frequency division multi...

Design of a 1-V 1-MS/s Track&Hold circuit based on the switched opamp approach

This paper presents the design and experimental results of a clock generator for high-frequency, continuous-time, converters. The circuit was fabricated in a -V, -nm CMOS technology along with two modulators intended for the digitisation of UWB signals. The clock generator is based on a PLL frequency synthesiser with a low phase noise LC Voltage-controlled oscillatror (VCO). This kind of oscillator achieves the required low jitter specification with a substantial lower power consumption than a conventional ring VCO. In order to save die area, the VCO was made to operate at four times the desired clock frequency of MHz, and a compact multi-layer inductor was used. A system clock with a cycle-to-cycle jitter of only of its period is obtained. The total circuit area is and the resulting power consumption is .

EFFECT OF FINITE AMPLIFIER BANDWIDTH AND EXCESS LOOP DELAY IN A PARALLEL CT ΔΣ ADC FOR OFDM UWB RECEIVERS

The design and implementation in a 1.2 V, 130 nm CMOS technology of an ADC intended for OFDM UWB signals is described. This ADC is based on parallel, continuous-time ΣΔ modulators, and employs an OFDM-optimized NTF, implemented using a 3rd order lowpass and a 4t order bandpass modulator. Both are CRFB structures which use active-RC integrators. “Early DAC” clocking is used to reduce the GBW of opamps. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15 dB DR for QPSK modulation.