J. Arias

A 1-GHz, multibit, continuous-time, delta-sigma ADC for Gigabit Ethernet

In this work the design of a continuous-time @D@S modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5MHz and 8, resulting in a clock frequency of 1GHz. It was designed and implemented in a standard 90nm CMOS technology. The active area of the modulator measures 0.0207mm^2. It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8mW from a nominal power supply of 1V.

Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator

A detailed analysis of the impact of a hysteretic quantizer on a multibit, Sigma-Delta modulator has been carried out in this paper. Both discrete-time and continuous-time modulators have been considered. A qualitative modeling of the hysteretic quantizer based on a hysteretic block followed by an ideal quantizer was proposed. Due to the hysteresis effect, the quantizer output signal is delayed and distorted with respect to the quantizer input signal, where the delay causes a phase-shift independent on the signal frequency. Yet, the effect of the hysteresis depends on the input signal amplitude. This model was validated by using system-level simulations for a second order, 3-bit, discrete-time Sigma-Delta modulator. A linear model for hysteresis was derived by assuming a narrow hysteresis cycle. The quantizer input signal plays a fundamental role in the discussion. In order to include this signal into the linear analysis some approximations are proposed. The quantizer output signal is decomposed by the use of the Fourier series analysis only into the in-phase and quadrature components (with respect to the input signal) whose Fourier series coefficients can be analytically calculated. A quantitative analysis for both a second order, 3-bit, DT and CT Sigma-Delta modulators including a hysteretic quantizer was carried out. For the CT modulator, finite GBW in amplifiers, excess loop delay, and a hysteretic quantizer were considered separately and combined. A good agreement with both system-level simulations and experimental results is found, despite the approximations considered for the quantizer input signal.

Design of a current-mode continuous-time Sigma-Delta modulator with exponential feedback for improved jitter rejection

In this article a current-mode, second-order, CT Sigma-Delta modulator operating at a sampling frequency of 25 MHz and with an oversampling ratio of 64 has been designed. The modulator consists of current-mode, differential integrators based on a single-stage folded cascode topology and switched capacitors DACs cells generating exponential feedback waveforms. The modulator was analysed in detail from both a system- and a circuit-level point of view. A ‘short’ exponential DAC pulse, namely, an exponential pulse whose time constant is lower than the pulse width, was used to improve jitter rejection. Modulator feedback coefficients were analytically derived for an exponential feedback waveform. Jitter considerations paying special attention to its impact on CT Sigma-Delta modulators were presented, and two different contributions distinguished: independent jitter and accumulated jitter. Finally, functional- and transistor-level simulations have been accomplished to obtain significant features of the modulator performance.

A 1.2V, 130nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers

The design and implementation in a 1.2V, 130nm CMOS technology of a parallel continuous-time @S@D modulator for OFDM UWB signals is described. Once the parallel architecture and the metrics used are presented, the NTF is optimized and implemented using a third order lowpass and a fourth order bandpass modulator. Both are CRFB structures which use active-RC integrators. Then, the circuital blocks are discussed and some comments about the test set-up are given. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15dB DR for QPSK modulation over a signal bandwidth of 528MHz, with a 62.3mW power consumption.

Design of a 1-V 1-MS/s Track&Hold circuit based on the switched opamp approach

A very low voltage solution for the realization of the hold capacitor in a Track&Hold circuit based on an open-loop architecture is introduced. The circuit is a modification based on the switched opamp approach of the Track&Hold circuit using Miller Capacitance. Simulations show that the circuit is able to operate at 1V 1MS/s with a Total Harmonic Distortion of −64 dB @ 100 kHz and a very low power consumption of 80 µW.

A Switched Opamp-Based Bandpass Filter: Design and Implementation in a 0.35 μm CMOS Technology

A fully differential SC bandpass filter (central frequency, 58 kHz; Q = 15; and voltage gain, 8) based on the switched-opamp approach is designed and implemented in this work. The filter operates from a single 1 V supply voltage and is realized in a 0.35 μm CMOS technology. It has been characterized with a sampling frequency of 1 MHz and its power consumption is about 230 μW. As a main internal filter component, an appropiate switched opamp was also designed. Its common-mode feedback circuit was implemented by using an error amplifier and sampling of the output common-mode voltage is carried out by applying a DC offset to level shift the common-mode sample. It provides an accurate common-mode output for a wide temperature and supply voltage ranges.

Enhanced modelization of ion implant simulation in compound semiconductors

Abstract An efficient binary collision approximation ion implant code with enhanced prediction capabilities is presented. It includes recent improvements in physical models for compound semiconductors. It uses only one fitting parameter for low dose implantations. A periodic ab initio full bond electron density for the target is used. Damage accumulation is supported using a modified Kinchin–Pease model. To speed-up the code a refined algorithm for statistical noise reduction is also included in a three-dimensional case, including the lateral and shallow zones. The agreement with experiments is good for different target materials. A comparison with experimental SIMS results for several projectiles and targets is presented.

Design of a CMOS fully differential switched-opamp for SC circuits at very low power supply voltages

This paper presents a fully differential opamp design based on the switched-opamp approach. The common mode feedback of the proposed opamp only works on the output stage in order to allow a fast turn-on. The opamp was designed in a 0.35 /spl mu/m CMOS technology and is able to operate from a single 1 V supply.

Study of non-ideal effects in a CT ΣΔ modulator with decaying exponential feedback waveforms

In this article, a detailed theoretical analysis of the impact of finite gain-bandwidth product (GBW) in amplifiers, excess loop delay, and a hysteretic quantiser on a second order, 3-bit, continuous-time sigma-delta (CT ) modulator with decaying exponential feedback pulses has been accomplished. A “short” exponential pulse – namely, an exponential pulse whose time constant is lower than the pulse width – was used in order to improve jitter rejection. An overall noise transfer function (NTF) that includes the effect of the three non-ideal effects was analytically calculated using the modified Z-transform method. The evolution of the NTF poles and zeroes locus in the z-plane is obtained when these effects are taken into account separately or combined. System-level simulations have been also carried out in order to validate the proposed theoretical study. The stability of a modulator with “short” exponential feedback pulses is higher than that of a modulator with rectangular ones when finite GBW or excess loop delay are included. Finally “short” exponential pulses and “narrow” rectangular ones are proved to be equivalent from the stability viewpoint.

LC-based clock generator for high-frequency, continuous-time, ΔΣ ADCs

This paper presents the design and experimental results of a clock generator for high-frequency, continuous-time, converters. The circuit was fabricated in a -V, -nm CMOS technology along with two modulators intended for the digitisation of UWB signals. The clock generator is based on a PLL frequency synthesiser with a low phase noise LC Voltage-controlled oscillatror (VCO). This kind of oscillator achieves the required low jitter specification with a substantial lower power consumption than a conventional ring VCO. In order to save die area, the VCO was made to operate at four times the desired clock frequency of MHz, and a compact multi-layer inductor was used. A system clock with a cycle-to-cycle jitter of only of its period is obtained. The total circuit area is and the resulting power consumption is .