Jesús Tabero

A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management

A novel technique is proposed for the management of a two-dimensional run-time reconfigurable device in order to get true hardware multitasking. The proposed technique uses a Vertex List Set to keep track of the available free area, and of the candidate locations to place the arriving tasks. Each Vertex List describes the contour of each unoccupied area fragment in the reconfigurable device. Several heuristics are proposed to solve the problem of selecting one of the vertices to place the task. The heuristic that gives best results is based on a novel fragmentation metric. This metric estimates for each alternative location the suitability of the resulting free device area to accept future incoming tasks. Finally, we show that our approach, with a reasonable complexity, gives better results, in terms of device fragmentation and efficiency, than other techniques.

Task placement heuristics based on 3D-adjacency and look-ahead in reconfigurable systems

To get efficient HW management in 2D reconfigurable systems, heuristics are needed to select the best place to locate each arriving task. We propose a technique that locates the task next to the borders of the free area for as many cycles as possible, trying to minimize the area fragmentation. Moreover, we combine it with a look-ahead heuristic that allows delaying the scheduling of a task to the next event, increasing the solution search space

Allocation heuristics and defragmentation measures for reconfigurable systems management

A novel technique is proposed for the management of a 2D reconfigurable device in order to get true hardware multitasking. We use a Vertex List Set to keep track of the free area boundary. This structure contains the best candidate locations for the task, and several heuristics are proposed to select one of them, based in fragmentation and adjacency. A Look-Ahead heuristic that anticipates the next known event is also proposed. A metric is used to estimate the fragmentation status of the FPGA, based on the number of holes and their shape. Defragmentation measures are taken when needed.

2D defragmentation heuristics for hardware multitasking on reconfigurable devices

This paper focuses on the fragmentation problem produced in 2D run-time reconfigurable FPGAs when hardware multitasking management is considered. Though allocation heuristics can take fragmentation into account when a new task arrives, the free area becomes inevitably fragmented as the tasks finish and exit the FPGA. The main contributions of our work are a fragmentation metric able to estimate when the FPGA fragmentation status has become critical, and several heuristics to decide when to perform defragmentation and how to perform it. This defragmentation heuristics can be of a preventive kind, driven by alarms that fire when isolated islands appear or a high fragmentation status is reached. It can be also an on-demand process produced when a task allocation fails though there is enough free area in the FPGA to accommodate it.

ASAP, towards a PARIS instrument for space

The technological aspects of the Altimetric and Scatterometric Applications of PARIS (ASAP) sensor are presented in this paper. This sensor is based on the PARIS concept, which makes use of GPS signals reflected on the oceans surface in order to measure the surfaces properties (altitude and roughness). The ASAP instrument is a hardware real-time PARIS receiver with the aim of being an intermediate step between the airborne GOLD-RTR receiver developed at our institute and a future spaceborne PARIS instrument.

Modular fault tolerant processor architecture on a SoC for space

Abstract Due to configurability feature and increasingly complex architecture, FPGAs have brought advantages to many applications such as avionics and safety critical aerospace, allowing in system reconfiguration after launch. Commercial FPGAs suffer from radiation-induced failures, which are provoked by high-energy particles in space; for this reason, fault tolerant techniques are necessary to harden these devices. This paper presents a design of a fault tolerant multicore processor architecture based on a novel modular voting strategy that fits in FPGAs and System-on-Chip (SoC) devices with an even number of processors. This architecture is implemented within a Commercial off-the-shelf (COTS) SoC that will allow to be used safely in space missions. To harden the fault tolerance of the embedded multicore processor architecture different fault tolerance techniques are combined.

SEFI Protection for Nanosat 16-Bit Chip Onboard Computer Memories

Plans to launch miniaturized satellite missions have been increasing in the last few years. Space missions like these are exposed to radiation, which is a cause of errors in electronic systems. Memories are one of the electronic systems that need special attention. Radiation effects in memories include single-event upsets (SEUs), multiple cell upsets, and single-event functional interrupts (SEFIs). In this paper, two solutions are presented to protect a nano/pico satellite onboard computer memory prototype with 16-bit data words against SEFIs and SEUs. The prototype uses a 32-bit memory interface, organized in two 16-bit chips. The approach to provide the error-correction capabilities is based on orthogonal latin square codes. The results show that the area and delay introduced by the solutions are acceptable. When a SEFI affects one of the chips, the solutions are able to recover the information using the remaining data.