Julio Septién

A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management

A novel technique is proposed for the management of a two-dimensional run-time reconfigurable device in order to get true hardware multitasking. The proposed technique uses a Vertex List Set to keep track of the available free area, and of the candidate locations to place the arriving tasks. Each Vertex List describes the contour of each unoccupied area fragment in the reconfigurable device. Several heuristics are proposed to solve the problem of selecting one of the vertices to place the task. The heuristic that gives best results is based on a novel fragmentation metric. This metric estimates for each alternative location the suitability of the resulting free device area to accept future incoming tasks. Finally, we show that our approach, with a reasonable complexity, gives better results, in terms of device fragmentation and efficiency, than other techniques.

Task placement heuristics based on 3D-adjacency and look-ahead in reconfigurable systems

To get efficient HW management in 2D reconfigurable systems, heuristics are needed to select the best place to locate each arriving task. We propose a technique that locates the task next to the borders of the free area for as many cycles as possible, trying to minimize the area fragmentation. Moreover, we combine it with a look-ahead heuristic that allows delaying the scheduling of a task to the next event, increasing the solution search space

A method for area estimation of data-path in high level synthesis

This paper describes a new method to estimate the area of data paths generated during a High Level Synthesis (HLS) process, when the information concerning the circuit is not yet complete. Our method is more accurate and considers more factors than those used by other HLS systems of which we are aware. Our main concern is the interconnection area, often neglected by HLS systems, which has a strong influence on the final circuit area being optimized, as well as a high dependency on the technology used and on the circuit area itself. Predicting the area of a design layout with accuracy is important because it allows one to foresee whether the design will satisfy the area constraints, and will lend the allocator towards the best design among several possibilities with guarantees. Our estimations of the final standard-cell layout area are similar, or even more accurate, than those obtained following methods used by low-level design systems, which have much more information available. Due to the performance penalty their relatively high complexity will produce, these methods are unusable in an HLS system exploring a wide design space. Our estimation, on the contrary, has a low complexity and can be repeated time and again as the HLS design space is searched.

3D FPGA resource management and fragmentation metric for hardware multitasking

This research work presents a novel proposal to get hardware multitasking in 3D FPGAs. Such architectures are still academic, but recent advances in 3D IC technologies allow foreseeing true 3D FPGAs in the near future. Starting from models for the 3D FPGA and for the tasks, an efficient technique for managing the 3D reconfigurable resources is proposed. This technique is based on a vertex-list structure in order to maintain information about the free space available on the FPGA at a given time moment. Moreover, a novel 3D fragmentation metric, based on cubeness of the free FPGA volume, is explained. And finally, several vertex-selection heuristics, a simpler one based on space adjacency and a more complex one based on space and time adjacency, are explained and their performance compared by some experiments.

Allocation heuristics and defragmentation measures for reconfigurable systems management

A novel technique is proposed for the management of a 2D reconfigurable device in order to get true hardware multitasking. We use a Vertex List Set to keep track of the free area boundary. This structure contains the best candidate locations for the task, and several heuristics are proposed to select one of them, based in fragmentation and adjacency. A Look-Ahead heuristic that anticipates the next known event is also proposed. A metric is used to estimate the fragmentation status of the FPGA, based on the number of holes and their shape. Defragmentation measures are taken when needed.

2D defragmentation heuristics for hardware multitasking on reconfigurable devices

This paper focuses on the fragmentation problem produced in 2D run-time reconfigurable FPGAs when hardware multitasking management is considered. Though allocation heuristics can take fragmentation into account when a new task arrives, the free area becomes inevitably fragmented as the tasks finish and exit the FPGA. The main contributions of our work are a fragmentation metric able to estimate when the FPGA fragmentation status has become critical, and several heuristics to decide when to perform defragmentation and how to perform it. This defragmentation heuristics can be of a preventive kind, driven by alarms that fire when isolated islands appear or a high fragmentation status is reached. It can be also an on-demand process produced when a task allocation fails though there is enough free area in the FPGA to accommodate it.

Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs

This paper presents a constant complexity and fast algorithm for the management of run-time reconfigurable resources by an operating system with extended hardware multitasking functionality. Our algorithm manages a two dimensional reconfigurable device by dividing the resource area into four partitions with different sizes. Each partition has an associated queue where the hardware manager places each arriving task depending on its size, shape, deadline requirements and the state of queues. It is possible to merge partitions for tasks not fitting any partition. The sizes of the partitions may be adapted to different circumstances.

Hardware allocation in FIDIAS system

A system oriented to the design of the datapath and the control of a digital system from a behavioral description and written in a high-level language is presented. The system module charged with the subtask of datapath allocation is shown in detail. The source code for this project is written in C language and runs on an HP9000/300 workstation under HP-US. GKS and X-Windows standards are used for graphics display and user interaction.<<ETX>>

An approach to minimal-time scheduling of micro-operations

Abstract The scheduling of operations is a major topic in the synthesis of digital systems from high level algorithmic specifications. Here we propose an approach which performs useful optimizations.

Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking

This paper explains a new technique to estimate free area fragmentation, when hardware multitasking is being considered on a 2D FPGA. The importance of a good fragmentation metric is stated, as well its use as allocation heuristic and as defragmentation alarm. We present a new fragmentation metric based on the relative quadrature of the free area perimeter, showing examples of how it behaves with one or several holes and also with islands. Finally, we show how it can be used as cost function in a location selection heuristic, each time a task is loaded in the FPGA. Experimental results show that though it maintains a low complexity, this metric behaves better than most of the previous ones, discarding a lower amount of computing volume when the FPGA supports a heavy task load.