Jhon Jhy Liaw

LAYOUT FOR MULTIPLE-FIN SRAM CELL

Cell structure for dual port SRAM

Interconnect structure for integrated circuits

Method for improving threshold voltage stability of a MOS device

Cell layout for SRAM FinFET transistors

ROM CELL CIRCUIT FOR FINFET DEVICES

STRUCTURE AND METHOD FOR SRAM CELL CIRCUIT

Fully Balanced Dual-Port Memory Cell

High speed sensing amplifier for an MRAM cell

Top and sidewall bridged interconnect structure and method