Ji Hoon Jang

Compression Accelerator for Hadoop Appliance

In this paper, we propose an accelerator for Hadoop appliances. Data servers receive significant data traffic because of several services based on networks. Processing such big data requires sufficient communication bandwidth for big data management. In order to increase communication bandwidth, compression algorithms are adopted in Hadoop appliances, although additional computation overhead is required. Our accelerator compresses data from a PCIe (Peripheral Component Interconnect Express) interface, thus reducing the size of data that should be transmitted through a network. As a result, computation overhead of the main processor in a server is decreased and communication bandwidth is increased.

Accelerating forex trading system through transaction log compression

In this paper, we propose the hardware architecture for high-speed transaction logging of forex trading system. In forex trading market, the trading volume of currencies is growing larger every year. In order to provide real-time processing of large volume and high availability service, we focused on the two types of the workload, where the bottleneck occurs, and conducted workload analysis. The bottleneck between the application server and the internal hard disk is caused by the overhead from storing the transaction logs, due to the bandwidth limitation of a hard disk. Our key idea is to suppress an overhead of the transaction logging through the compression of the transaction logs. Implementation result demonstrates the feasibility of our proposal for increasing the bandwidth through the log compression.

Intra-Body Communication for Personal Area Network

The intra-body communication uses the human body as a conducting wire, providing the simplicity and the security. Although the communication distance is limited within a body-area, it is useful on the construction of personal area network. In this paper, we introduce our prototype intra-body communication module using the FPGA. The proposed system has the FSK modulator and the demodulator. These modulation methods are chosen after body-channel analysis. The experimental results demonstrate the feasibility of our intra-body communication module for establishing the PAN (Personal Area Network).

In-Time Transaction Accelerator Architecture for RDBMS

In this paper, we propose a hardware architecture for in-time transaction accelerator that reduces the bottlenecks between the DB server and the DB storage in margin FX trading system’s RDBMS (Relational Database Management System). In-time transaction accelerator located between the DB server and the DB storage analyzes and processes the queries used for margin FX trading system by co-processing of the CPU and the FPGA. The accelerator analyzes the patterns and the consistency of the queries to reduce the total database access in order to increase the RDBMS’s throughput.

mrGlove: FPGA-Based Data Glove for Heterogeneous Devices

In this paper, we propose a glove based equipment (mrGlove) for a user interface that controls a device through hand motion recognition. The mrGlove provides more user experience compared to conventional devices such as a keyboard and a touchscreen. Our mrGlove is able to control a heterogeneous device (Windows or Android) that offers more convenience and user experience. Experimental results prove the feasibility of our proposal for enhancing convenience and user experience by obtaining control of an object through motion recognition in the PC and the smartphone.

An FPGA Based Compression Accelerator for Forex Trading System

In this paper, we propose an FPGA based hardware accelerator for forex trading system. In the forex trading market, the trading volume of currencies is growing larger every year. In order to provide a real-time processing of large volume and high availability service, we focused on the two types of workload, where a bottleneck occurs. The bottleneck between an application server and an internal hard disk is caused by the overhead from storing the transaction logs, due to the bandwidth limitation of a hard disk. Our key idea is to suppress the overhead of transaction logging through the high throughput hardware compression. Compared to software compression, our hardware accelerator scored 6x better performance in compression throughput.

Design of Hardware Accelerator for Lempel-Ziv 4 (LZ4) Compression

Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65nm CMOS technology.

Live demonstration: An FPGA based hardware compression accelerator for Hadoop system

Hadoop is an emerging data application for the big data processing. In Hadoop system, data compression is a significant part in processing big data effectively. Achieving this in software requires significant compute processing. In this paper we present the detailed design of a hardware compression accelerators. We also measure the performance of the hardware accelerators. Our analysis shows that hardware acceleration has the potential to improve the data compression by as much as 12x. As a result, our hardware accelerator provides a real time data processing of big data.

Design of an EMG signal recognition system for human-smartphone interface

In this paper, we propose an EMG signal recognition system for human-smartphone interface. Proposed system provides user experience and interface to control a smartphone application, recognizing pattern of surface electromyography (sEMG) in real time. For classifying events according to transition of the sEMG, classification checks whether an event is active or not in accordance with algorithm to compare the threshold value of the sEMG signal. Proposed system is portable and is able to be integrated into the SoC thanks to a part of proposed system in the field programmable gate array (FPGA). We expect proposed system can be exploited in the entertainment field and wearable device market.