Seung Eun Lee

CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition

As smart mobile devices become pervasive, vendors are offering rich features supported by cloud-based servers to enhance the user experience. Such servers implement large-scale computing environments, where target data is compared to a massive preloaded database. CogniServe is a highly efficient recognition server for large-scale recognition that employs a heterogeneous architecture to provide low-power, high-throughput cores, along with application-specific accelerators.

Area and power-efficient innovative congestion-aware Network-on-Chip architecture

This paper proposes a novel Network-on-Chip architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also provides a power-efficient solution for interconnection network scenarios. Diagonally-linked mesh NoC that uses wormhole packet switching technique implements a high-performance NoC platform to meet both cost and power consumption requirements. The proposed architecture uses an adaptive quasi-minimal routing algorithm so that it can improve average latency and saturation traffic load owing to its flexibility and adaptiveness. Based on these features, a congestion-aware routing algorithm is proposed to balance traffic load so as to alleviate congestion caused by high throughput network activities. Simulation results show that saturation load is improved dramatically for various traffic patterns. Implementation results also show that employing diagonal links is a more area-efficient method for improving network performance than using large buffers. It is shown that congestion-aware router requires negligible cost overhead but provides better throughput. Finally, simulation results also reveal that power consumption in the proposed architecture outperforms traditional mesh networks.

Pipelined CPU Design With FPGA in Teaching Computer Architecture

This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on time. The goal of the project is to educate students effectively via hands-on learning, rather than having them achieve a complete and flawless CPU design. This study reveals that 21 MIPS instructions are enough to achieve the purpose. With the addition in 2010 of the properly enforced scheduling and the FPGA system, many more students successfully completed the class project than was the case in 2009. A student survey and the independent samples t-test reveal the effectiveness of the methodology with the FPGA system. This work differs from previous work in that the devised project requires the implementation of a real CPU instead of utilizing simulators or just experimenting with ready-made complete CPU models.

Accelerating Histograms of Oriented Gradients descriptor extraction for pedestrian recognition

Abstract Pedestrian recognition is an emerging visual computing application for embedded systems. In one usage model, a vehicle mounted camera acquires image from road and a pedestrian recognition system automatically recognizes and alarms information on the road preventing traffic accidents. Achieving this in software on embedded systems requires significant compute processing for object recognition. In this paper, we identify the hotspot function of the workload on an embedded system that motivates acceleration and present the detailed design of a hardware accelerator for Histograms of Oriented Gradients descriptor extraction. We also quantify the performance and area efficiency of the hardware accelerator. Our analysis shows that hardware acceleration has the potential to improve the hotspot function. As a result, user response time can be reduced significantly.

Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms

In an SoC, building local storage in each accelerator is area inefficient due to the low average utilization. In this paper, we present design and implementation of Buffer-integrated-Caching (BiC), which allows many buffers to be instantiated simultaneously in caches. BiC enables cores to view portions of the SRAM as cache while accelerators access other portions of the SRAM as private buffers. We demonstrate the cost-effectiveness of BiC based on a recognition MPSoC that includes two Pentiumℒ cores, an Augmented Reality accelerator and a speech recognition accelerator. With 3% extra area added to the baseline L2 cache, BiC eliminates the need to build 215KB dedicated SRAM for the accelerators, while increasing total cache misses by no more than 0.3%.

Low-Power, Resilient Interconnection with Orthogonal Latin Squares

A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55% energy reduction, with only a small area overhead and no loss in reliability.

Secure communication system for wearable devices wireless intra body communication

This paper explains how intra-body communication can be used to establish a secure communication channel for wearable devices. Intra-body communication transfers data using the human body as its conductor. This paper describes a secure communication system that supports multiple wearable slave devices. Our prototype, wearable on the wrist, has an integrated processor to control the intra-body communication module. Instead of using radio transmission, the module uses the human body, thus maximizing the security of transmitted signals.

mGlove: Enhancing User Experience through Hand Gesture Recognition

In this paper, we propose hand gesture recognition equipment (mGlove) for a user interface which provides more effective experience compare to conventional devices such as a keyboard and a mouse. Communication module establishes the communication channel between mGlove and a host PC. Experimental results demonstrate the feasibility of our proposal for enhancing user experience by gaining full control of an avatar through hand gesture recognition.

Deadlock-free XY-YX router for on-chip interconnection network

Specifically, based on the observation that a response is always preceded by a request in multi-processor SoCs, this letter proposes a novel deadlock-free XY-YX router for on-chip network performance improvement. In order to avoid deadlock, we add additional physical channels in the horizontal direction and optimize the priority of output channel allocation. Simulation results show the enhancement in the throughput of an NoC.

Reducing L1 caches power by exploiting software semantics

To access a set-associative L1 cache in a high-performance processor, all ways of the selected set are searched and fetched in parallel using physical address bits. Such a cache is oblivious of memory references software semantics such as stack-heap bifurcation of the memory space, and user-kernel ring levels. This constitutes a waste of energy since e.g., a user-mode instruction fetch will never hit a cache block that contains kernel code. Similarly, a stack access will not hit a cacheline that contains heap data.n We propose to exploit software semantics in cache design to avoid unnecessary associative searches, thus reducing dynamic power consumption. Specifically, we utilize virtual memory region properties to optimize the data cache and ring level information to optimize the instruction cache. Our design does not impact performance, and incurs very small hardware cost. Simulations results using SPEC CPU and SPECjapps indicate that the proposed designs help to reduce cache block fetches from DL1 and IL1 by 27% and 57% respectively, resulting in average savings of 15% of DL1 power and more than 30% of IL1 power compared to an aggressively clock-gated baseline.