Ji-Hye Jang

Design of an EEPROM for a MCU with the Wide Voltage Range

In this paper, we design a 256 kbits EEPROM for a MCU (Microcontroller unit) with the wide voltage range of 1.8 V to 5.5 V. The memory space of the EEPROM is separated into a program and data region. An option memory region is added for storing user IDs, serial numbers and so forth. By making HPWs (High-voltage P-wells) of EEPROM cell arrays with the same bias voltages in accordance with the operation modes shared in a double word unit, we can reduce the HPW-to-HPW space by a half and hence the area of the EEPROM cell arrays by 9.1 percent. Also, we propose a page buffer circuit reducing a test time, and a write-verify-read mode securing a reliability of the EEPROM. Furthermore, we propose a DC-DC converter that can be applied to a MCU with the wide voltage range. Finally, we come up with a method of obtaining the oscillation period of a charge pump. The layout size of the designed 256 kbits EEPROM IP with MagnaChips 0.18 ㎛ EEPROM process is 1581.55 ㎛ × 792.00 ㎛.

Design of low-power and high-speed receiver for mobile display module

We newly proposed a low-power and high-speed mobile display digital interface (MDDI) client receiver in this paper. The receiver was designed as a low-power circuit which had a constant current dissipation over variations of the common-mode voltage (VCM) and power supply voltage, and was able to operate at a rate of 450 Mbps or above under the conditions of a power supply of 3.3 V and a temperature range of -40 to 85degC. A test chip was manufactured with the 0.35 mum CMOS process. When a test was done with a function generator, the data receiver and data recovery circuit were functioning normally.

Design of a 256-KBit EEPROM IP for touch-screen controllers

We propose a compact design having low-power and high-speed EEPROM for touch-screen controller ICs. To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. 256-KBit EEPROM IP is designed using MagnaChips 0.18µm EEPROM process. The layout size of the designed 256-KBit EEPROM IP is 1765.05µm × 691.71µm.

Design of 1-kbit antifuse OTP memory IP using dual program voltage and its measurement

In this paper, we design a 1-kbit antifuse OTP (one time programmable) memory IP which is used for power management ICs. A conventional antifuse OTP cell using a single VPP (positive program voltage) has a problem about applying a higher voltage than the breakdown voltage to thin gate oxides and securing the reliability of MV (medium voltage) devices which are thick gate transistors at the same time. Thus, we design and measure a 1-kbit antifuse OTP breaking down hard the thin gate oxides by using dual program voltage: VPP (positive program voltage) and VNN (negative program voltage). It is designed with Dongbu HiTeks 0.18 µm BCD (Bipolar-CNOS-DMOS) process and its yield is 80% when three series of continuous programming are done on 56 test dies at the following program voltages : VPP=8V and VNN=−2V.