Young-Hee Kim

Reliability of Pb-free preplated leadframe under atmosphere and accelerated aging test

Atmospheric corrosion of Pb-free preplated leadframe (PPF) finish, which causes unacceptable appearance due to discoloration, has been meticulously investigated. The discoloration appears particularly on the shoulder, tip, and sidewall of the leadframe, where bare Cu is directly exposed to the given environments. Such Cu exposure is attributed to the forming and trimming process of the PPF. It is found that the geometrical feature of the ragged shear edge on the sidewall of the PPF is dependent on the condition of a cutting tool. There is a porous Ni layer on the Cu substrate. It is also found that the tarnish products consist of cuprous oxide (Cu/sub 2/O) and cuprous sulfide (Cu/sub 2/S). The depth profile reveals a thick Cu oxidation layer over cuprous sulfide, which implies that the integrity of a dual inline package assembled with the PPF is susceptible when exposed to a relatively higher humidity and sulfur-involved environments. To reproduce the atmospheric corrosion, a variety of laboratory aging tests that include the mixed flowing gas (MFG) test was used. Except the MFG test, the laboratory corrosion that yields Cu oxidation only is not identical to the atmospheric corrosion. As results, electronic devices assembled with the PPF must be sealed into a moisture-barrier bag to extend the shelf life during storage, if particularly they are exposed to relatively harsh circumstances, higher humidity in H/sub 2/S atmosphere.

Physical simulation for verification and OPC on full chip level

In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.

Design of 1.2 GeV synchrotron light source for X-ray lithography at Samsung Heavy Industries

An 1.2 GeV electron storage ring being designed at Samsung Heavy Industries Daeduk R&D Center is optimized for X-ray lithography works for high density semiconductor devices and micro-machining. The lattice is a variation of a FODO arrangement with four quadrupole doublets. The circumference of 57.6 m includes four 2.1-m-long straight sections and two 3.09-m-long dispersion-free straight sections making the synchrotron a racetrack shape. Two dispersion-free straight sections are located between the doublets and reserved for diagnostics and insertion devices. The harmonic number is 96 and the corresponding RF frequency is 449.654 MHz. The critical X-ray wavelength from sixteen 1.16-m-long bending magnets is 9.55 /spl Aring/ and a superconducting wiggler is also included in the design considerations. The major features of the light source will be described.

Highly sensitive and fast scanner focus monitoring method using forbidden pitch pattern

Forbidden pitches that are introduced under certain illumination conditions can have extremely narrow depth of focus (DOF), so that when a lithographic pattern is transferred to a wafer, the forbidden pitch should be removed from the layout. However, the sensitivity of this narrow DOF can be utilized to monitor focus changes in the scanner system itself. In this paper, a newly developed focus monitoring method utilizing the forbidden pitches is introduced and the sensitivity and advantages of this method are discussed in detail.

Wafer-induced reading error in metal sputtering process

For higher density devices electric performances have been focused more than the others. In the case of metal sputtering process some of machine makes local asymmetric deposition across the wafer. In this study, a couple of overlay reading errors which comes from asymmetric metal deposition has been studied in terms of photo process. As a result, scaling error could be reduced down to a certain amount with the optimization of overlay reading marks. However it will not be cleared no matter what kinds of mark are used as long as overlay marks are asymmetry. A symmetric sputtering should be the only way to figure out this problem. In order to make total product, related processes have to be concerned as well.

Applications of industrial electron accelerators at Samsung Heavy Industries

An industrial electron beam accelerator has been developed at Samsung Heavy Industries with the collaboration of Seoul National University and Russian Budker Institute of Nuclear Physics. The accelerator is a high voltage accelerator using rectifiers and able to deliver 40 mA of 1 MeV electrons in CW mode. Functionally, the accelerator is an electron irradiation processing device and an electron beam scanning system is employed for the uniform irradiation of the electron beam through the extraction window of the size 980 mm/spl times/75 mm. The industrial applications of the electron irradiation processes include combustion flue gas purification process, treatment of industrial waste water containing refractory pollutant, treatment of semiconductor devices, and radio-chemical processes. The major features of the device and its industrial applications will be described.

Investigating the performance of directional boundary layer model through staged modeling method

Generally speaking, the models used in the optical proximity effect correction (OPC) can be divided into three parts, mask part, optic part, and resist part. For the excellent quality of the OPC model, each part has to be described by the first principles. However, OPC model cant take the all of the principles since it should cover the full chip level calculation during the correction. Moreover, the calculation has to be done iteratively during the correction until the cost function we want to minimize converges. Normally the optic part in OPC model is described with the sum of coherent system (SOCS[1]) method. Thanks to this method we can calculate the aerial image so fast without the significant loss of accuracy. As for the resist part, the first principle is too complex to implement in detail, so it is normally expressed in a simple way, such as the approximation of the first principles, and the linear combinations of factors which is highly correlated with the chemistries in the resist. The quality of this kind of the resist model depends on how well we train the model through fitting to the empirical data. The most popular way of making the mask function is based on the Kirchhoffs thin mask approximation. This method works well when the feature size on the mask is sufficiently large, but as the line width of the semiconductor circuit becomes smaller, this method causes significant error due to the mask topography effect. To consider the mask topography effect accurately, we have to use rigorous methods of calculating the mask function, such as finite difference time domain (FDTD[2]) and rigorous coupled-wave analysis (RCWA[3]). But these methods are too time-consuming to be used as a part of the OPC model. Until now many alternatives have been suggested as the efficient way of considering the mask topography effect. Among them we focused on the boundary layer model (BLM) in this paper. We mainly investigated the way of optimization of the parameters for the BLM since the feasibility of the BLM has been investigated in many papers[4][5][6]. Instead of fitting the parameters to the wafer critical dimensions (CD) directly, we tried to use the aerial image (AI) from the rigorous simulator with the electromagnetic field (EMF) solver. Usually that kind of method is known as the staged modeling method. To see the advantages of this method we conducted several experiments and observed the results comparing the method of fitting to the wafer CD directly. Through the tests we could observe some remarkable results and confirmed that the staged modeling had better performance in many ways.

High sensitive and fast scanner focus monitoring method using forbidden pitch pattern

Forbidden pitch which is introduced under a dipole illumination condition has extremely narrow DOF (Depth Of Focus). Therefore when a lithographic pattern is transferred on a wafer the forbidden pitch should be removed from the layout. However this narrow DOF behavior can be utilized to monitor a focus of scanner systems due to its sensitiveness to focus changes. In this paper, a newly developed focus monitoring method utilizing a forbidden pitch pattern will be introduced and the benefits and sensitivity of this method will be discussed in details.