Liyan Jin

Low-area 1-kb multi-bit OTP IP design

In this paper 1-kb multi-bit OTP IP, which is non-volatile memory, is designed for a power management IC. A conventional multi-bit OTP cell uses isolated NMOS transistor, but the cell size is large in the BCD process. So, PMOS transistor is used instead of the isolated NMOS transistor as antifuse, and the cell size is minimized by optimizing the size of PMOS transistor. In addition, an ESD protection circuit is added to prevent the case that any cell is programmed by high voltage at ESD test. The 1kb OTP IP is designed using Dongbus 0.18µm BCD process and the layout size of the IP is 160.490 × 506.255 µm 21.

Design of 1-Kb eFuse OTP Memory IP with Reliability Considered

In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the nonprogrammed eFuse is reduced from 728 ㎂ to 61 ㎂ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 ㏀ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).

Design of an EEPROM for a MCU with the Wide Voltage Range

In this paper, we design a 256 kbits EEPROM for a MCU (Microcontroller unit) with the wide voltage range of 1.8 V to 5.5 V. The memory space of the EEPROM is separated into a program and data region. An option memory region is added for storing user IDs, serial numbers and so forth. By making HPWs (High-voltage P-wells) of EEPROM cell arrays with the same bias voltages in accordance with the operation modes shared in a double word unit, we can reduce the HPW-to-HPW space by a half and hence the area of the EEPROM cell arrays by 9.1 percent. Also, we propose a page buffer circuit reducing a test time, and a write-verify-read mode securing a reliability of the EEPROM. Furthermore, we propose a DC-DC converter that can be applied to a MCU with the wide voltage range. Finally, we come up with a method of obtaining the oscillation period of a charge pump. The layout size of the designed 256 kbits EEPROM IP with MagnaChips 0.18 ㎛ EEPROM process is 1581.55 ㎛ × 792.00 ㎛.

Design of parallel backlight LED driver IC

This paper presents a LED(Light Emitting Diode) backlight driving system for automobile panels. A new scheme is presented and compared to the conventional scheme, and the simulation model for new scheme is presented and used to simulate the system. The study indicates the necessity of a technique for current equalization when using parallel LED arrays system1.

Design of low-power and high-speed receiver for mobile display module

We newly proposed a low-power and high-speed mobile display digital interface (MDDI) client receiver in this paper. The receiver was designed as a low-power circuit which had a constant current dissipation over variations of the common-mode voltage (VCM) and power supply voltage, and was able to operate at a rate of 450 Mbps or above under the conditions of a power supply of 3.3 V and a temperature range of -40 to 85degC. A test chip was manufactured with the 0.35 mum CMOS process. When a test was done with a function generator, the data receiver and data recovery circuit were functioning normally.

Design of 1-kbit antifuse OTP memory IP using dual program voltage and its measurement

In this paper, we design a 1-kbit antifuse OTP (one time programmable) memory IP which is used for power management ICs. A conventional antifuse OTP cell using a single VPP (positive program voltage) has a problem about applying a higher voltage than the breakdown voltage to thin gate oxides and securing the reliability of MV (medium voltage) devices which are thick gate transistors at the same time. Thus, we design and measure a 1-kbit antifuse OTP breaking down hard the thin gate oxides by using dual program voltage: VPP (positive program voltage) and VNN (negative program voltage). It is designed with Dongbu HiTeks 0.18 µm BCD (Bipolar-CNOS-DMOS) process and its yield is 80% when three series of continuous programming are done on 56 test dies at the following program voltages : VPP=8V and VNN=−2V.

Design and measurement of a small-area 512-Bit EEPROM

In this paper, a logic process based small-area 512-bit EEPROM IP for a passive RFID tag chip is designed. We propose a shared CG (Control gate) driver structure in the EEPROM core circuit for a small-area IP design. Devices of 3.3V are limited within 5.5V in the write mode to secure the endurance of 1,000 erase and program cycles as well as ten years of data retention. To meet the above conditions, we use a three-stage voltage level translator circuit in the CG driver. Also, we propose a DOUT buffer circuit to output a selected read datum by latching two words of BL (Bit line) data. The layout area of the designed 512-bit EEPROM IP with c-flash cells of Towers 0.18µm process is 373.96µm × 434.04µm. It is confirmed by the computer simulation that the power dissipation is 0.35 µW in the read mode, 13.76µW in the program mode, and 13.66µW in the erase mode, respectively. It is also confirmed by the experiment that the test chip is functioning normally.