Ji-Soo Park

Formation of CoTi barrier and increased thermal stability of CoSi2 film in Ti capped Co/Si(100) system

We investigated the formation of CoSi2 for Ti capped Co on (100) Si substrate with emphasis on the Co–Ti interaction and its effect on thermal stability. A 15 nm thick Ti capping layer is shown to improve the interfacial roughness and thermal stability of CoSi2 film grown on Si substrate compared with TiN capping. The increased uniformity of silicide/Si(100) interface is speculated to result from retarded Co–Si reaction by the formation of CoTi binary phase. And the high thermal stability can be explained by the fact that the amount of Ti atoms in CoSi2 film for Ti capping is much higher than what is in TiN capping. It is likely that the surface Ti diffuses rapidly into CoSi2 grain boundaries and slows down the agglomeration process, thereby increasing thermal stability while Ti in TiN capping did not.

High thermal stability and low junction leakage current of Ti capped Co salicide and its feasibility for high thermal budget CMOS devices

A thermally stable cobalt salicide has been fabricated using Ti-capping Co/Si system. A Ti-capping layer is shown to improve the interfacial roughness and thermal stability of CoSi/sub 2/ film grown on Si substrate comparing with TiN-capping. It is attributed to high amount of Ti atoms in Co disilicide film, which slow down the agglomeration. According to the results of salicided gate and junction, Ti capped CoSi, had stable characteristics when the thermal budget increased up to 850/spl deg/C for 90 min. Therefore, Ti-capping Co salicide structure can be acceptable to fabricate DRAM and LOGIC-embedded DRAMs.

Effect of Deposition Temperature and Sputtering Ambient on In Situ Cobalt Silicide Formation

An investigation of in situ cobalt self-aligned silicide (salicide) formation has been carried out with emphasis on the effect of the deposition temperature and the role of nitrogen atoms in the sputtering ambient. The cobalt (Co) layer was deposited at between 300 and 500°C in a mixed atmosphere of nitrogen and argon; the nitrogen volume percent [N 2 volume percent (v/o)] was varied from 0 to 10%. The addition of nitrogen atoms to the sputtering ambient resulted in a polymorphic change of the Co layer which was deposited on the SiO 2 substrate; from α-Co to β-Co. At the same time, it limited the surface mobility of the sputtered atoms, resulting in a decrease of grain size. Specifically, during Co deposition on a Si substrate at temperatures as high as 500°C, in situ cobalt silicide (CoSi) was formed. In that process, nitrogen atoms limited the available Co atoms involved in the reaction with the Si substrate, yielding the bilayer formation of β-Co/CoSi. As the N 2 v/o increased, the thickness of the overlying β-Co increased and that of the underlying CoSi decreased with improvement in the uniformity of the silicide film. It shows good selectivity with no overgrowth on the sidewall oxide, but also extremely uniform salicide on both the silicon and the polysilicon substrate. As a result, satisfactory electrical characteristics were obtained because of thin and uniform CoSi 2 salicide.

Characterization of the Dopant Effect on Dichlorosilane‐Based Tungsten Silicide Deposition

In this paper, the dopant (phosphorus) effects of polycrystalline silicon (polv-Si) on dichlorosilane-based tungsten silicide deposition have been studied with emphasis on the crystallinity of the WSi x film. The WSi x over doped poly-Si (polycide) was formed using an integrated cluster platform which was equipped with chambers for the deposition of the in situ doped poly-Si and the dichlorosilane-based tungsten silicide without vacuum break. It was found that the phosphorus atoms in poly-Si films enhance the dissociation of WF 6 , and thus yield a W excessive WSi x film having an amorphous feature. As the P concentration of the poly-Si is increased while the deposition temperature is decreased, the formation of the amorphous layer is facilitated. This systematic study reviews the correlations between the dopant in the underlying poly-Si and the structural, compositional, and electrical properties of the as-deposited and the annealed WSi x films. Finally, a successful integrated polycide process, avoiding such a dopant effect, has been suggested.

Formation of High Conductivity WSi x Layer and its Characterization as a Gate Electrode

A novel integrated clustered electrode for gate electrode application has been developed. This method includes a sequential deposition of in situ phosphorus doped polycrystalline silicon and dichlorosilane-based tungsten silicide films using a clustered platform without a vacuum break. The dopant atom, phosphorus, in the polycrystalline silicon substrate enhances the reduction of WF 6 , resulting in the formation of an amorphous layer (WSi 1.1 ) with a uniform thickness and a lower resistivity of 234 μΩ cm. Upon thermal annealing, the composition of the silicide was converted into WSi 2.2 with an accompanying thickness increase of the silicide. At the interface of WSi x /polycrystalline silicon, no defects due to the thickness change were observed at all, while the grain size and the resistivity of the silicide were measured to be 100-400 nm and about 36 μΩ cm, respectively. As a result of its application to a complementary metal oxide semiconductor device having a 0.25 μm minimum linewidth, the line resistance was three times lower than with the conventional WSi x . In addition, characteristics such as the dopant depletion of the gate electrode and the reliability of the gate oxide were superior to those of the conventional WSi x . This systematic study has also reviewed the correlation between the silicides structural properties and device performance.

In-situ barrier formation for high reliable W/barrier/poly-Si gate using denudation of WN/sub x/ on polycrystalline Si

We found that rapid thermal annealing treatment of amorphous WN/sub x//poly-Si resulted in denudation of nitrogen atoms with formation of low resistivity W and high reliable in situ barrier layer, simultaneously. Furthermore, electrical properties of denuded-WN/sub x//poly-Si gate were superior to those of conventional W/WN/sub x//poly-Si gate after selective oxidation and post heat-treatment.

Formation of epitaxial CoSi2 spike in Co/Si3N4/Si(100) system and its crystallographic structure

The formation of CoSi2 spike in the Co/Si3N4/Si(100) system and its crystallographic structure have been investigated. An annealing at 1050 °C caused not only agglomeration of Co film but penetration of Co agglomerates through the Si3N4 layer. The CoSi2 spike of B type epitaxial and twinned orientation of CoSi2[110]∥Si[110], Si(111)∥CoSi2(111) and Si(111)∥CoSi2(111) was formed in the Si substrate by the penetrated Co source. The formation of the epitaxial CoSi2 spike can be explained by the fast diffusion of Co atoms along defects in Si such as dislocations resulting from stress between the Si3N4 layer and the Si substrate.

Low-resistivity noble integrated clustered electrode (NICE) WSi/sub x/ polycide and its application to a deep sub-quarter micron CMOS

This paper is aimed at suggesting a new technique satisfying the requirement of future devices using a clustered platform, named NICE WSix. It consists of sequential deposition of in-situ doped poly and SiH/sub 2/Cl/sub 2/ (DCS)-based WSix, forming a WSix/poly-Si stacked gate. The resistivity of NICE WSix was 36 /spl mu//spl Omega//spl middot/cm after thermal annealing, which is three times lower than that of conventional WSix (Conv.WSix). Moreover, the thermal stability was found to be excellent. We have successfully applied this technology for 1 Giga-bit DRAM.

Dopant Effects on Lateral Silicide Growth in Self‐Aligned Titanium Silicide Process

The effects of sidewall material and implanted dopants have been investigated on the lateral silicide growth in self-aligned titanium silicide process. The SiO 2 sidewall spacer showed no lateral silicide growth and has a low leakage current between gate and source/drain up to silicidation temperatures of 750°C. This was found to be due to released oxygen from the SiO 2 sidewall spacer into titanium film, which impedes silicon diffusion over the SiO 2 . However, the Si 3 N 4 sidewall spacer showed dopant dependence of the lateral silicide growth and leakage current. This discrepancy between SiO 2 and Si 3 N 4 results from the fact that nitrogen has lower reactivity with titanium and less suppression of the lateral silicide growth than oxygen. The lateral silicide growth and leakage current in Si 3 N 4 decreased in the order of dopant species of B > BF 2 > As and P Released dopants from Si 3 N 4 can affect the silicon diffusion, and this is closely related to the reactivity of each dopant with titanium.

Simultaneous Formation of Shallow Junctions and Gate Doping for Dual Gate Structures Using Cobalt Silicone as a Dopant Source

The fabrication of high performance dual gate complementary metal oxide semiconductor (CMOS) devices has been demonstrated by dopant implantation into a self-aligned CoSi 2 layer, followed by a single drive-in annealing. By the optimization of polycrystalline Si (poly-Si) gate thickness and drive-in annealing conditions, it was shown that CMOS devices annealed at 900°C with gate poly-Si of 200 nm thickness gives simultaneous formation of shallow junction and gate doping for both n-channel MOS and p-channel MOS with a single drive-in annealing. CMOS devices fabricated with this technology exhibit good junction characteristics. In particular, there is no degradation from silicidation, implantation-induced damage, gate dopant depletion, or boron penetration. Also, high reliability of the gate oxide and low sheet resistance of CoSi 2 can be obtained. Therefore, it is suggested that simultaneous formation of shallow junction and gate doping using Co silicide as a dopant source is a promising technique for the fabrication of high performance dual gate CMOS devices.