Ji-Yong Um

A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits

A digital-domain calibration method is proposed for a split-capacitor DAC (split-CDAC) used in a differential-type 11-bit SAR ADC. It calibrates the nonlinearities of SAR ADC due to the DAC capacitance mismatch as well as the two parasitic capacitances connected in parallel with each of the bridge capacitor and the LSB bank of split-CDAC. The proposed ADC does not require any additional analog circuits for calibration, because it utilizes one of the two split-CDACs to measure the error codes of the other split-CDAC. During the normal A/D conversion step, the 11.5-bit raw SAR code output of ADC is added to the pre-measured error codes to generate the 11-bit calibrated output code. The analog block of the ADC was fabricated in a 0.13- μm CMOS process, and the digital block was implemented in a FPGA. The measured SNDR and SFDR are 61.6 dB (ENOB 9.93 bits) and 78 dB at the Nyquist rate with a 5 kHz sine wave input. INL and DNL are measured to be +0.96/-0.98 LSB, and +0.96/-0.97 LSB, respectively. This work extends the prior work by utilizing an additional 0.5-bit raw SAR code to eliminate the missing code, and by employing a temporal averaging with a FIR LPF to measure the error code reliably in spite of the supply noise.

24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area

Ultrasound imaging is widely used for medical diagnosis, because it is harmless to the human body and has real-time processing capability. Usually the focusing (beamforming) operation is performed for both TX and RX. The RX focusing is performed by an RX beamformer [1-5], which consists of delay elements and adders. Nowadays, digital beamformers (DBF) are mostly used for conventional ultrasound imaging because of high SNR. Recently, 2D ultrasound transducers have been introduced for 3D imaging. Since the 2D transducer has a huge number of transducer elements (e.g., 9216 for a 72×128 array), it cannot use DBF because of the huge number of required ADCs and wires inside the probe cable. Therefore, analog beamforming must be performed, at least at the front stage of the 2D transducer.In this work, where a 2D CMUT array is used, the maximum delay difference among transducer elements is 8μs with a maximum steering angle of 45° and a maximum focal depth of 15cm. The target sampling resolution is 6.25ns (λc / 53.3) with a carrier frequency of 3MHz. An analog-digital-hybrid architecture and a non-uniform sampling scheme are used for the RX beamformer of this work to achieve the wide dynamic range of delay time and small chip-area. The RX beamformer consists of 8 analog beamformers (ABF) followed by a single DBF, as shown in Fig. 24.8.1. An ABF performs the focusing operation for the input signals of the adjacent 8 channels to generate an analog output signal. The 8 analog output signals from the 8 ABFs are applied to the DBF. The DBF converts the 8 analog input signals into the 8 digital signals, and then performs the focusing operation on the 8 digital signals to generate a digital output signal for every focal point.

A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer

A single-chip 32-channel analog beamformer is proposed. It achieves a delay resolution of 4 ns and a maximum delay range of 768 ns. It has a focal-point based architecture, which consists of 7 sub-analog beamformers (sub-ABF). Each sub-ABF performs a RX focusing operation for a single focal point. Seven sub-ABFs perform a time-interleaving operation to achieve the maximum delay range of 768 ns. Phase interpolators are used in sub-ABFs to generate sampling clocks with the delay resolution of 4 ns from a low frequency system clock of 5 MHz. Each sub-ABF samples 32 echo signals at different times into sampling capacitors, which work as analog memory cells. The sampled 32 echo signals of each sub-ABF are originated from one target focal point at one instance. They are summed at one instance in a sub-ABF to perform the RX focusing for the target focal point. The proposed ABF chip has been fabricated in a 0.13- μm CMOS process with an active area of 16 mm 2. The total power consumption is 287 mW. In measurement, the digital echo signals from a commercial ultrasound medical imaging machine were applied to the fabricated chip through commercial DAC chips. Due to the speed limitation of the DAC chips, the delay resolution was relaxed to 10 ns for the real-time measurement. A linear array transducer with no steering operation is used in this work.

An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array

To reduce the memory area, a two-stage RX beamformer (BF) chip with 64 channels is proposed for the ultrasound medical imaging with a 2D CMUT array. The chip retrieved successfully two B-mode phantom images with a steering angle from -45° to +45°, the maximum delay range of 8 μs, and the delay resolution of 6.25 ns. An analog-digital hybrid BF (HBF) is chosen for the proposed chip to utilize the easy beamforming operation in the digital domain and also to reduce chip area by minimizing the number of ADCs. The chip consists of eight analog beamformers (ABF) for the 1st-stage and a digital beamformer (DBF) for the 2nd-stage. The two-stage architecture reduces the memory area of both ABF and DBF by around four times. The DBF circuit is divided into three steps to further reduce the digital FIFO memory area by around twice. Coupled with the non-uniform sampling scheme, the proposed two-stage HBF chip reduces the total memory area by around 40 times compared to the uniform-sampling single-stage BF chip. The chip fabricated in a 0.13- μm CMOS process occupies the area of 19.4 mm2, and dissipates 1.14 W with the analog supply of 3.3 V and the digital supply of 1.2 V.

A Design Guide of 3-stage CMOS Operational Amplifier with Nested Gm-C Frequency Compensation

An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.

Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC

A digital-domain calibration is proposed for a split-capacitor DAC of a 0.5 V 11 bit 10 kS/s differential-type SAR ADC. The calibration improves the linearity of ADC, especially INL by +1.59/-1.71 LSB, SFDR by 19.1 dB, and SNDR by 5.0 dB (ENOB by 0.83 bits). It compensates both the mismatch among binary-weighted capacitors and the errors due to parasitic capacitance of bridge-capacitor and LSB bank. No extra calibration DAC is required in this work, because one of the two differential DAC branches is used to measure errors of the other DAC branch. Measurements on the fabricated chip with a 0.13 mm CMOS process show INL +0.78/-0.89 LSB, DNL +0.75/-0.89 LSB, SNDR 61.7 dB (ENOB 9.96 bits), and SFDR 81.8 dB at the Nyquist rate. The power consumption and FoM of analog block are 560 nW and 55 fJ/conversion-step, respectively.

A single-chip time-interleaved 32-channel analog beamformer for ultrasound medical imaging

This paper proposes a single-chip time-interleaved 32-channel analog beamformer for ultrasound medical imaging. The proposed analog beamformer circuit consists of multiple sub analog beamformers which are time-interleaved for beamforming of multiple focal points on a scan line. Each sub analog beamformer executes beamforming for an assigned focal point on a scan line sequentially by sampling and summing the ultrasound echo signals of 32 channels. The proposed 32-channel analog beamformer circuit was fabricated in a single chip with an active area of 15.75 mm2 in a 0.13 μm standard CMOS process. The total power consumption of the chip is 150 mW with a 1.2V supply. The delay resolution of the implemented analog beamformer circuit is 1/200 of the ultrasound carrier period. The analog beamformer operation was successfully verified through measurements by applying the emulated ultrasound echo signals taken from a commercial ultrasound imaging device through commercial DAC chips to the fabricated chip.

A Gate-Leakage Insensitive 0.7-V 233-nW ECG Amplifier using Non-Feedback PMOS Pseudo-Resistors in 0.13-μm N-well CMOS

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 ㎐ to 480 ㎐, the midband gain programmable from 48.7 ㏈ to 59.5 ㏈, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 ㎻ in a 0.13 ㎛ CMOS process at the supply voltage of 0.7 V.

A Single-Stage 37 dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Medical Imaging

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closedloop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gaincontrol block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].

Time-interleaved sample clock generator for ultrasound beamformer application

A sample clock generator (SCG) for application in a 32-channel ultrasound receiver beamformer is proposed. The RX beamformer samples the echo signals at delayed timings to align them in the time domain before summing them. The proposed SCG employs a dual counter and comparator scheme to generate delayed sampling clocks with 4.17 ns delay control resolution. The SCG is implemented using Verilog RTL code and the analog block of the beamformer was modeled with ideal sample and hold circuits. The beamformer was simulated using a mixed-signal simulator and the results verify the feasibility of the proposed scheme.