Jia-Hua Hong

Low-Power Analog Integrated Circuits for Wireless ECG Acquisition Systems

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

A programmable implantable micro-stimulator SoC with wireless telemetry: Application in closed-loop endocardial stimulation for cardiac pacemaker

The use of closed-loop implantable telemetry devices [1,2] is increasing as recent clinical studies have shown their efficiency and usefulness in detecting and treating various cardiac arrhythmias. In this paper, we present a single-chip closed-loop system providing closed-loop feedback of sensed cardiac patterns. This device promises more optimized stimulation parameters to cure rapid arrhythmias compared with open-loop devices. Our system incorporates more functionality comparing with the conventional micro-stimulators, yet consumes less power. It is powered by implanted rechargeable batteries periodically charged by radio-frequency (RF) coupling. This improvement of the powering system can prevent improper device operation or shutdown due to RF coupling and loading variations. Furthermore, this system eliminates the need for periodic surgery for battery replacement and improves quality of life of the patient.

Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist

A synthesis tool consisting of coefficient synthesis of architecture, circuit specifications synthesis, and CMOS operational-amplifier (op-amp) synthesis for discrete-time sigma-delta modulators (SDMs) is presented. In circuit specifications synthesis, several major circuit non-idealities are discussed and modeled. A precise performance prediction with a new design flow of specification synthesis is proposed. A hybrid design methodology composed of equation-based and simulation-based approaches for synthesizing fully differential two-stage and folded-cascode op-amps in 0.35 µ m technology is also presented. Experimental results show that the peak signal-to-noise and distortion ratio (PSNDR) of the fourth-order feed-forward (FF) SDM with an oversampling ratio (OSR) of 64 and a bandwidth of 20KHz estimated by the proposed synthesis tool is 94.19dB, and the result of the circuit simulation with folded-cascode op-amp is 93.03dB. The estimated PSNDR of the third-order multiple-feedback (MF) SDM with an OSR of 32 and a bandwidth of 256KHz is 59.52dB, and the HSPICE simulation result is 55.39dB.

Analog front-end circuit with low-noise amplifier and high-pass sigma-delta modulator for an EEG or ECoG acquisition system

The present paper proposes an analog front-end (AFE) circuit, including only one low-noise amplifier with chopping techniques and one high-pass sigma-delta modulator (HPSDM), which can be applied as a sensing circuit for electroencephalogram or electrocorticogram (ECoG) signal acquisition systems. The low-noise amplifier, which has a close-loop gain of 20 V/V and CMRR of 109.6 dB, is implemented by a differential difference amplifier with feedback pseudo-resistors and capacitors. The HPSDM is implemented in a feed-forward architecture with an order of 3, an oversampling ratio of 128, and a 1-bit quantizer under a sampling frequency of 51.2 kHz. The TSMC 0.18 μm 1P6M CMOS process is used in the entire AFE circuit with a supply voltage of 1.2 V and power consumption of 28.7 μW. Within the maximum range of ECoG signals, the simulated SNR and SFDR of the entire AFE circuits are 70.8 and 73 dB, respectively.

Wide dynamic-range sigma-delta modulator with adaptive feed-forward coefficients

A novel adaptive approach for sigma-delta modulators (SDMs) to improve dynamic range significantly is proposed. Based on adapting the signal power gain of SDMs, several dynamic-range curves can be obtained. The cascade of integrators with distributed feedback (CIFB) structure is used to demonstrate the basic idea. A systematic approach with the proposed optimising algorithm is used to acquire the boundary constraints. Therefore, a wider dynamic range can be achieved without changing the original architecture. The simulation results reveal that the proposed method under coefficient spread of 60 000 can improve dynamic ranges by 39 and 20 dB for a fourth-order CIFB structure with an oversampling ratio (OSR) of 32 and 64, respectively. Moreover, a fourth-order SDM with CIFB structure and OSR of 32 under the coefficient spread of 3 455 with less hardware is implemented by switched-capacitor circuits, and a 16 dB dynamic range improvement is revealed to agree with the proposed method.

Burst-pulse control of microstimulator for bladder controller

This paper presents a method for the control of the variable burst biphasic pulse of a bladder stimulator. The stimulator is used to pass current through the tissue and to generate useful action potentials. The binary-weighted digital-to-analog converter combined with a current mirror has been employed as a microstimulator because of its higher linearity without requiring the decoding of digital inputs. Given that the use of a biphasic pulse could prevent ion-charge accumulation in tissues, two pairs of switches controlled by different clock phases are implemented to provide the biphasic electrical stimulation pulses. According to measurement results, the pulse frequency can be programmed between 1.49 Hz and 47.66 Hz, the burst frequency can be controlled from 190.8 Hz to 763 Hz, and the pulse width can be adjusted between 21 μs and 325 μs. These stimulation parameters are adapted by the clock divider and by the number of controlled bits in the digital circuits.

An Analogue Front-End System with a Low-Power On-Chip Filter and ADC for Portable ECG Detection Devices

Medical diagnostic instruments can be made into portable devices for the purpose of home care, such as the diagnosis of heart disease. These assisting devices are not only used to monitor patients but are also beneficial as handy and convenient medical instruments. Hence, for reasons of both portability and durability, designers should reduce the power consumption of assistant devices as much as possible to extend their battery lifetime. However, achieving the low power requirement of the ECG sensing and the processing board for the ECG with commercial discrete components (A21-0003) is difficult because the low power consumer electronics for ECG acquisition systems are not yet available. With the help of the integrated circuit technology, the power-saving requirement of portable and durable equipment gives circuit designers the impetus to reduce the power consumption of analogue front-end circuits in ECG acquisition systems. In addition, the analogue front-end circuits, which are the interface between physical signals and the digital processor, must be operated at a low-supply voltage to be integrated into the low-voltage system-on-a-chip (SOC) system (Eshraghian, 2006). Therefore, the chapter will present two design examples of low-voltage (1 V) and low-power (<1 W) on-chip circuits including a low-pass filter (LPF) and an analogue-to-digital converter (ADC) to demonstrate the possibility of developing the low-voltage low-power ECG acquisition SOC

Wireless brain signal acquisition circuits for body sensor network

The paper presents the proposed wireless brain signal acquisition circuits for body sensor network. Considering the power-efficient communication in the body sensor network, the required low-power analog integrated circuits (ICs) are developed for a wireless brain signal acquisition system. To acquire the electroencephalogram (EEG) signal, this paper proposes an analog front-end (AFE) circuit, including only one low-noise amplifier with chopping techniques and one high-pass sigma-delta modulator (HPSDM), which can be applied as a sensing circuit for EEG signal acquisition systems. To transmit the EEG signal through wireless communication, a quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and up-conversion mixer are also developed. In the receiver, a 2.4 GHz fully integrated CMOS radio-frequency front-end is also implemented. The circuits have been implemented to fit the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless EEG acquisition systems have been fabricated using a 0.18 μm TSMC CMOS standard process. The measured results reveal that the proposed low-power analog front-end ICs can be used for the wireless brain signal acquisition.

A Performance Prediction Method with an Equation-Based Behavioral Model for a Single-Bit Single-Loop Sigma-Delta Modulator

An equation-based behavioral model has been developed to predict the real performance of a single-loop single-bit Sigma Delta Modulator SDM. By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switched-capacitor circuits, but the real performance of the SDM can also be predicted. The switched-capacitor circuits according to the required circuit specifications are employed to design a fourth-order feed-forward FF SDM with an over-sampling ratio OSR of 64 and a bandwidth of 10kHz using a TSMC 0.35i¾µm CMOS process. The measurement results reveal that the SDM with an input frequency of 2.5kHz and a supply voltage of 3.3V can achieve a dynamic range of 90dB and a spurious-free dynamic range SFDR of 85dB under the signal bandwidth of 10kHz and a sampling frequency of 1.28MHz, respectively. The precision of the equation-based behavioral model has been validated by experimental measurements, and its inaccuracy is less than 4%.