Jia-Ming Lin

Source-end design and failure study for ESD enhancement of 60 V nLDMOS devices

In this work, ESD immunity enhancement for the HV n-channel LDMOS with source-end discrete islands fabricated by a TSMC 0.25 μm 60 V process was investigated. An nLDMOS device always has poor ESD capability. If discrete n+ islands are formed in the source end of an nLDMOS transistor, the It2 value of this DUT is upgraded by 4.92% as compared with that of the reference nLDMOS. Meanwhile, if an nLDMOS is embedded with an SCR with an npn (pnp) stripe manner in the drain end, the corresponding It2 can be enhanced by 14.8% (30%) as compared with those of the reference nLDMOS. Moreover, if source-end discrete islands are designed into an npn-arranged (pnp-arranged) nLDMOS-SCR, the maximum It2 values are improved by 24.6% (>282.5%). Then, an nLDMOS incorporating discrete n+ islands in the source end will be effective in enhancing ESD reliability.

ESD-improvement comparisons of HV n-/p-LDMOS components by the bulk modulations

HV n-/p-LDMOS devices with the source-side extending into bulk-region to evaluate the electrostatic-discharge (ESD) protection robustness by a TSMC 0.25 µm 60 V process are investigated in this paper. After a systematic analysis, the trigger voltage (Vt1) values of the n-LDMOS with the source-side extending into the bulk-end either by uniformly or non-uniformly distributed manners that had decreased with the bulk space interval increasing (the source-side area ratio increased). However, the second breakdown current (It2) values had increased obviously with this interval increasing. On the other hand, the trigger voltage (Vt1) of the p-LDMOS with the source-side extending into bulk-region uniformly had a minimum value being 71.783 V. And, the holding voltage (Vh) values decreased a little about 3.2% with the bulk-side modulation. Meanwhile, the second breakdown current (It2) values increased at least about 23%. Moreover, both the trigger voltage (Vt1) and the holding voltage (Vh) of n-/p-LDMOS with uneven bulk modulation were smaller than the uniform modulation. And, the second breakdown current (It2) improvement can be found that the n-LDMOS (2030%) are better than the p-LDMOS (43.1%). Therefore, the ESD-robustness improvement of n-LDMOS by the bulk uneven modulation is obvious in this work. Hence, the n-LDMOS with the bulk uneven modulation could increase the parasitic bulk-resistance (Rbulk) efficiently to achieve high anti-ESD ability.

ESD reliability improvement of the 0.25-µm 60-V power nLDMOS with discrete embedded SCRs separated by STI structures

In this paper, the electrostatic-discharge (ESD) robustness improvement by modulating the drain-side embedded SCR of an HV nLDMOS device is investigated via a TSMC 0.25 μm 60 V process. After a systematic layout design and data analysis, it can be found that the holding voltage (Vh) of an nLDMOS with a parasitic SCR “npn”-arranged type & thin oxide (OD) discrete (i.e. separated by the shallow-trench isolation (STI) structure) distribution in the drain-side have greatly increased with the parasitic SCR OD decreasing. Therefore, a high Vh value in the OD discrete parameter 2 (DIS-2) can be obtained about 13.3 V. On the other hand, the trigger voltage (Vt1) values and the holding voltage (Vh) values of the nLDMOS DUTs with a parasitic SCR “pnp”-arranged type & OD discrete distribution in the drain-side are slowly increased with the parasitic-SCR OD decreasing. The best Vh value in the “pnp”-arranged type & OD discrete parameter 2 (DIS-2) is about 14.4 V. Meanwhile, the secondary breakdown current (It2) values of this type are greater than 7 A except for the OD discrete parameter 2 and 3. Therefore, an appropriate layout of nLDMOS embedded with a drain-side “pnp” arranged type & OD discrete distribution that can yield high ESD and latch-up (LU) robustness levels.

Design on ESD robustness of source-side discrete distribution in the 60-V high-voltage nLDMOS devices

The electrostatic-discharge (ESD) protection capability of HV nLDMOS devices with the source-side engineering by a TSMC 0.25μm 60-V is investigated in this paper. It can be found that a pure nLDMOS device has a poor anti-ESD ability (It2 = 1.833A). At the same time, if an nLDMOS was embedded with an SCR npn-(pnp-) arranged type in the drain-side, the corresponding secondary breakdown-current values are promoted 19.4% (24.8%) as comparing with a traditional nLDMOS. Furthermore, if the source discrete methodology is applied for the nLDMOS-embedded SCR npn-(pnp-) arranged type, the maximum secondary breakdown current value are promoted 24.1% (>281.9%). Finally, it can be concluded that a discrete distribution in the source region of a pure nLDMOS will upgrade the anti-ESD capability effectively, and it is especially for the nLDMOS-SCR pnp-arranges type.

ESD reliability improvement by the source-discrete placement in a 45-V pLDMOS-SCR (npn-type)

In this paper, Electrostatic-Discharge (ESD) reliability study of 45-V HV pLDMOS devices with the source-side discrete islands is investigated. A pure pLDMOS transistor is always frail in ESD harms (It2= 0.107-A). However, if a pLDMOS device with two embedded SCRs (drain side npn-arranged); the corresponding It2 current can be upgraded to 0.644-A. Furthermore, as a pLDMOS-SCR (npn-arranged stripe type) extra with the source discrete technique, the trigger voltage (Vt1) values of these pLDMOS-SCR devices have slowly increased with the OD-rows number decreased. And, a highest Vt1 value on DIS-3 of 48.49-V can be obtained. Meanwhile, the best secondary breakdown current (It2) value is 4.032-A. Then, a source discrete technique is good for ESD robustness in these pLDMOS-SCR compound devices.

ESD protection design for the 45-V pLDMOS-SCR (p-n-p-arranged) devices with source-discrete distributions

An evaluation of electrostatic-discharge (ESD) reliability by changing the source-end layout of 45-V HV pLDMOS devices is investigated in this paper. After testing and systematic analysis, it can be found that a traditional pLDMOS sample is always very weak in ESD issues (It2= 0.107-A). At the same time, if a pLDMOS with a stripe type embedded SCR (p-n-p-arrangement in the drain-end); the corresponding secondary breakdown-current value can be improved about 501.9% as comparing with a pure pLDMOS. Furthermore, when a pLDMOS-SCR possesses the p-n-p-arranged stripe type and source discrete technique, the trigger voltage (Vt1) values of these samples are all about 45-V ~ 47-V. Next, the holding-voltage (Vh) values were slowly increased with the OD-rows number decreased. Also, the secondary breakdown-current (It2) capabilities are upgraded to 3-A ~ 4-A except for S_DIS 3. Eventually, it can be concluded that a discrete distribution in the source region of a pLDMOS-SCR will upgrade the anti-ESD capability effectively as this embedded SCR is p-n-p-arranged in the drain side.

Impacts on the anti-ESD/ anti-LU immunities by the drain-side superjunction structure of HV/ LV nMOSFETs

Experimental comparisons between the reference pure sample and composite devices with a super-junction (SJ) structure in the drain-side of low-voltage and high-voltage MOSFETs are investigated in this paper. From testing results, the drain-side engineering of super-junction methodology has negative (positive) impacts on the anti-ESD capability in the LV nMOSFET (HV nLDMOS) devices. Then as a result, the layout type of nMOSFET-SJ (nLDMOS-SJ) has a lower (higher) It2 and Vh values. Eventually, it can be summarized that this drain-side SJ structure of MOSFET device is a bad (good) choice for the anti-ESD/ anti-LU robustness improvements for the LV (HV) process.