Hung-Wei Chen

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow. This dual-WF approach provides excellent Vth roll-off immunity in the short-channel regime that allows properly positioning the long-channel device Vth. Enhanced 193nm immersion lithography has enabled the stringent requirements of the 22/20nm ground rules. Reliability of our advanced HK/MG stack is promising. Excellent SRAM static noise margin at 0.45V is reported.

Channel backscattering characteristics of strained PMOSFETs with embedded SiGe source/drain

Channel backscattering ratios of PMOSFETs with various embedded SiGe source/drain structures are analyzed in terms of the scattering theory. We found that both the backscattering ratio and injection velocity are greatly influenced by the location and recess depth of SiGe source/drain. Although the strain-enhanced injection velocity is beneficial to the current gain, the accompanying backscattering ratio increase adversely impacts the overall performance, and therefore a trade-off exists between injection velocity and backscattering ratio during the optimization of such strain technique. The mechanism of increased backscattering ratio under uniaxial compressive strain is also investigated

Effects of Mechanical Uniaxial Stress on SiGe HBT Characteristics

In this work, we investigate the characteristics of collector current (I_C) and breakdown voltage (BV_CEO) of SiGe HBTs under the mechanical uniaxial stress by a four-point bending apparatus. DeltaI_c and DeltaBV_CEO is found to be strain-polarity dependent, and there is a trade-off between DeltaI _c and DeltaBV_CEO at the same stress condition

Characterizing the Channel Backscattering Behavior in Nanoscale Strained Complementary Metal Oxide Semiconductor Field-Effect Transistors

This work investigates the impact of different uniaxial strain polarities on channel backscattering in nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET). Two carrier statistics, nondegenerate and degenerate-limited, are employed to extract the channel backscattering ratio, ballistic efficiency, and related backscattering factors. While the channel length scales down and the channel stress level increases further, the modulation of channel backscattering ratio, i.e., improved (degraded) by uniaxial tensile (compressive) strain, becomes more prominent. This observation holds true under both carrier statistics, which implies that the nondegenerate case with simple mathematics can be fairly used for evaluation. In addition, the correlation between strain-enhanced mobility gain and drain current improvement is found to be predicted well by the ballistic efficiency deduced with the nondegenerate carrier statistics.

Top antireflective coating process for 193 nm lithography

Presently for 248 nm lithography, a bottom antireflective coating (BARC) is main method for obtaining better throughput. In the coming 193 nm lithography, substantial critical dimension (CD) control will be required, so that process requirements for improved CD uniformity include minimizing the reflectivity swing amplitude of a resist/BARC/substrate system. Although swing amplitude could be suppressed by using BARC, a simulation clarified that swing amplitude could not be optimized to 0%. This paper evaluates the potential improvements with the addition of an aqueous based top antireflective coating (TARC) to a 193 nm process. A recent material, AZ/sup (R)/ AQUATAR-VI, has been formulated with a refractive index and coating thickness optimized for the process. This TARC is resistant to intermixing with the resist and is removed during the normal develop operation. A logic IC with 0.13 μm design rules will be the primary test vehicle, concentrating on gate levels.