Shen Li Chen

Impact of Drain-Side nWell Engineering on ESD Robustness in 0.35μm LV MOSTs

A multi-finger nMOST is widely used as an electrostatic discharge (ESD) protection device especially in the input/output pads. However, the contact-spiking leakage phenomenon in an MOST are seriously impacted the ESD capability. Therefore, one drain-side engineering is investigated in this paper, i.e., by adding a negative-type well (nWell) structure in the drain-side of device, hoping to avoid contact-spiking issues to enhance ESD reliability. The nWell width variations will be explored the influence on snapback parameters of ESD devices in a 0.35μm 3.3V low voltage (LV) process. However, after a systematic analysis, it is found that adding an nWell structure in the drain-side will lower ESD capability (It2 value) about 24% for this process. And, as compared with the original reference DUT, adding any nWell in the drain-side will make the Vh value slightly decreasing about 1%.

The SCR Protection Circuit Evaluation in HV DEMOS Devices

The electrostatic discharge (ESD) failure of power drain-extended MOS (DEMOS) devices, the protection circuit SCR, and a DEMOS with SCR protection circuit will be investigated in this paper. The ESD immunity of the DEMOS was very poor under the human-body model (HBM) testing. Here we discuss how to design an ESD good SCR device. Eventually, the ESD immunity of DEMOS test sample with an SCR circuit can significantly improve device ESD performance.

ESD-Reliability Analysis and Strategy of the GaN-Based Light-Emitting Diodes

Compounds such as GaN, ZnSe, and SiC are the compounds that currently hold the most potential in developing blue light-emitting diodes (LEDs) and blue laser diodes (LDs). Speaking of the physical property, the gallium nitride belongs to a direct bandgap material with an obviously super luminous efficiency; therefore, the gallium nitride has the dominate tendency than that of others materials. Although the gallium nitride has excellent physical properties, but in actually it is suffered many challenges during the manufacture process. Especially, it is extremely sensitive to the electrostatic discharge (ESD) threat. In other words GaN diodes generally exhibit very low anti-ESD capabilities when in HBM, MM reversed bias modes. These LEDs in the MM stress situation, its ESD immunity level usually is only about 50-V extremely low anti-ESD ability. Therefore, in this paper, GaN LED DUTs will be stressed and investigated under HBM and MM pulses bombardments, and the aim of this work is to describe a detailed investigation of the factors that limit the robustness of GaN-based LEDs under ESD transient events; finally they will provide some countermeasures in ESD reliability consideration.

Influences of MOS Device Characteristic under Different Oxygen-Dose Participations in the Silicon Substrate

A silicon substrate is the starting point of producing the semiconductor component, so that the quality of semiconductor substrate is very important during the VLSI fabrication. In this paper, we will evaluate the influence of MOS device characteristics under different oxygen impurities in silicon substrates. In the course of silicon substrate pulling process by Czochralski method, the defect and impurity will be existed; the oxygen atom will be induced substrate dislocations and affected the substrate quality. In this work, different oxygen doses will be used in wafer to study the impacts on MOS CV curve characteristic, interface trap charge characteristic, ID-VDS curve, ID-VGS curve, and threshold voltage behaviors of MOS devices.

ESD Failure Analysis and Robustness Design in Vertical-Diffused MOS Transistors

This paper deals with a detailed study of ESD failure mode and how to strengthen of the VDMOS used for power applications. The ESD post-zapped failure of power VDMOS transistors due to HBM, MM, and CDM stresses are examined in this work. Through standard failure analysis techniques by using EMMI and SEM were applied to identify the failure locations. The MM failure mode in this power MOSFET was caused by the gate oxide breakdown near n+ region in the source end as an ESD zapping. And, the ESD failure damage under HBM and CDM stresses were caused by the gate material molten near the gate pad and tunneled through the oxide layer into silicon epitaxial layer. Furthermore, the ESD robustness designs of power VDMOS transistors are also addressed in this work. The first ESD incorporated design is Zener diodes back-to-back clamping the gate-to-source pad, and on the other hand, another one excellent design contains two Zener diodes clamping the gate-to-source and gate-to-drain terminals of a VDMOS, respectively.

ESD and LU Immunities of LV nMOSFETs by the Drain-Contact Variations

The non-uniform turned-on issue of a multi-finger GGnMOS is deeply affect the ESD robustness. This paper introduces a drain-side engineering: by removing the drain contacts to increase the Ron value of a GGnMOS. However, after the actual systematic testing, it can be concluded that removing the drain contacts will obviously decrease the ESD capability and this way is not good for the ESD ability. The It2 value in the Type-1.1 DUT becomes only 56% of the reference group (Ref. DUT). The It2 value will increase as along with the contact number to increase. Meanwhile, the layout pattern of the contacts concentrated around the both ends will have a higher It2 value, i.e., (It2)type2 > (It2)type1, the increasing percentage of It2 values of Type-2 as compared with Type-1 can be up to 8.63%. So, a drain-contact arrangement will strongly affect the device ESD ability.

Implementation of a High Reliability IGBT Power Device

The insulating-gate bipolar transistor, IGBT, is a power component which is developed in the medium power and medium frequency. It inherently integrates the structures of a power bipolar transistor and a power MOSFET, and then it has better performance in many applications. Advantages of this device are the high current density, the outstanding breakdown voltage, as well as the excellent operating frequency and so on. And, it might make up the shortcoming of MOSFETs or BJTs utilized separately. In this paper, a smart IGBT device is developed by using the semiconductor process and device simulation tools. Therefore, a relationship between the depth of drift region, doping concentration, and breakdown voltage in an IGBT will be investigated in this work. Eventually, this device will be with the 200V breakdown voltage and 20A on-state driving current capability. Meanwhile, the ESD and latch-up (LU) protection structures will be accomplished in this study.

A Contactless Sensing Analysis of a CUP Wafer

The detected structures in a CUP wafer by sensing (leakage) analysis are presented in this paper. The pad structures are designed by the ADS2009 & TSMC 0.18um CMOS processes design rules, and use some electrostatic discharge (ESD) protection devices and circuits under these pads. Furthermore, the signal will be passed through these ESD devices or circuits on the top-metal pad as a sinusoidal, square, or ESD pulse waveform being injected. It is found that during an ESD occurred situation, a strong signal coupling can be sensed by the ESD protection circuits.

A Novel Method to Extract Carrier Mobility and Threshold Voltage in High-Voltage DDD MOSFETs

In this work, we apply the Hauser technique and combine a newer inversion layer charge model to extract the effective channel carrier mobility (μeff) and threshold voltage (Vth) of several high-voltage DDD MOSFETs with different dimensions in channel length and width. This paper proposes and demonstrates that our new method is a novel and efficient to extract the carrier mobility and threshold voltage in the DDD MOSFET, meanwhile, the extracted data is well consistent with UT model. And, only the extracted values by our new method and BCV method can clearly reflect the narrow-width effect which results from the so called LOCOS isolation technique. Therefore, it is clearly to see that our extraction technique can exactly reflect the device characteristics in high-voltage DDD MOSFETs.

Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.