Jialin Zhao

A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS

This paper presents a continuous-time ΔΣ modulator targeted at optimizing power efficiency for input bandwidth exceeding 50 MHz. Delay in the feedback path is carefully minimized and traditional techniques for DAC mismatch correction and excess loop delay compensation are both replaced with digital schemes. Power is also minimized by relaxing loop filter BW requirements and using a power efficient opamp topology. The modulator achieves 73 dB dynamic range (DR) in 80 MHz BW while consuming 23 mW. The peak SNR is 70 dB and the peak SNDR is 67.5 dB, resulting in FOMs of 168 dB and 163 dB based on DR and SNDR, respectively.

15.5 A 930mW 69dB-DR 465MHz-BW CT 1–2 MASH ADC in 28nm CMOS

The width of RF bands commonly used for cellular telecommunications has grown from 35-to-75MHz for 2G/3G/4G platforms to 100-to-200MHz for todays LTE, and the desire for relaxed image-rejection filtering has pushed the direct IF sampling frequencies to 300+ MHz. This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC IC that achieves 69dB of DR over a 465MHz signal bandwidth with a combined power consumption of 930mW from ±1.0V/1.8V supplies. The ADC IC is implemented in 28nm CMOS and achieves a peak SNDR of 65dB, a small-signal noise-spectral density (NSD) of -156dBFS/Hz, and a figure-of-merit (FOM) of 156dB over a signal bandwidth of 465MHz.

A −89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique

This brief presents a power and area efficient way to measure the feedback DAC static mismatch error in a multi-bit continuous-time delta-sigma modulator. By sequentially forcing each DAC element output in the designed scheme, the mismatch errors among DAC elements can be measured digitally using the ADC itself. The measured errors are then corrected using a two-parameter calibration DAC that tracks temperature variations. An ADC test chip is fabricated in 28-nm CMOS process and it demonstrates IMD3 <−89 dBc with two −9-dBFS tones at 180/190 MHz at room temperature, and 8 dB variation across −10 °C to 120 °C.

Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS

This paper presents an adaptive digital noise cancellation filter (DNCF) using cross-correlation (XCORR) developed for continuous-time (CT) multi-stage noise-shaping (MASH) ADCs. The XCORR engine continuously estimates the transfer functions of ΔΣ sub-loops and updates the coefficients for the DNCF. An ADC prototype with this engine is built in 28nm CMOS and it achieves 72dB of dynamic range over 440MHz BW, with a total power of 1.25W from 1V and 1.8 V supplies. Comparing to a power-up least-mean squares (LMS) engine, the XCORR-based adaptive DNCF achieves 2dB better noise cancellation across up to 10% supply variations.