Yunzhi Dong

A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS

We present design and measurement details for a 0-3 multi-stage noise-shaping (MASH) ADC that achieves a dynamic range of 88 dB over 53 MHz signal bandwidth. The ADC utilizes a zeroth-order front-end, i.e., a 17-level flash ADC, to perform a coarse quantization and a third-order 7-level continuous-time ΔΣ back-end to digitize the residue error of the front-end. The ADC achieves the high thermal noise power efficiency of a continuous-time feedforward ΔΣ modulator and the flat signal transfer function of a flash ADC. The test chip, implemented in a 28 nm CMOS process, clocks at 3.2 GHz. The average noise spectral density with small input signals is -167 dBFS/Hz and the dynamic range is 88 dB. The test chip ADC consumes a total power of 235 mW from triple power supplies of 0.9/1.8/-1.0 V. The thermal-noise figure-of-merit, defined as FOM = DR + 10log 10 (BW/P) is 171.6 dB.

15.5 A 930mW 69dB-DR 465MHz-BW CT 1–2 MASH ADC in 28nm CMOS

The width of RF bands commonly used for cellular telecommunications has grown from 35-to-75MHz for 2G/3G/4G platforms to 100-to-200MHz for todays LTE, and the desire for relaxed image-rejection filtering has pushed the direct IF sampling frequencies to 300+ MHz. This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC IC that achieves 69dB of DR over a 465MHz signal bandwidth with a combined power consumption of 930mW from ±1.0V/1.8V supplies. The ADC IC is implemented in 28nm CMOS and achieves a peak SNDR of 65dB, a small-signal noise-spectral density (NSD) of -156dBFS/Hz, and a figure-of-merit (FOM) of 156dB over a signal bandwidth of 465MHz.

Advances in high-speed continuous-time delta-sigma modulators

The maximum clock rate of continuous-time ΔΣ modulators has increased dramatically over the past several years, showing that continuous-time systems can operate at higher rates than their discrete-time counterparts. This paper outlines the circuits and architectures that have led to these improvements and presents an analysis of the maximum clock rate of continuous-time ΔΣ modulators when limited by the metastability error of the internal flash ADC, resulting in a simple relationship between metastability error and SNR. A circuit simulation technique is also presented that helps analyse high-speed continuous-time systems to identify and correct non-idealities in the modulators transfer functions.

29.2 A 235mW CT 0-3 MASH ADC achieving −167dBFS/Hz NSD with 53MHz BW

The trend for ADCs in wireless communication infrastructure is increased bandwidth with little or no relaxation in noise density or power consumption. The historical expectation of system designers is a noise spectral density (NSD) of -157dBFS/Hz with a power consumption of 0.5W. This expectation is a difficult one to meet with existing ADC architectures when the system bandwidth is 100MHz as demanded by standards such as LTE-A. The 0-3 continuous-time (CT) MASH [1-2] ADC described in this paper allows a direct-conversion receiver with the requisite bandwidth to be constructed, with 10dB lower noise than established benchmarks.

A −89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique

This brief presents a power and area efficient way to measure the feedback DAC static mismatch error in a multi-bit continuous-time delta-sigma modulator. By sequentially forcing each DAC element output in the designed scheme, the mismatch errors among DAC elements can be measured digitally using the ADC itself. The measured errors are then corrected using a two-parameter calibration DAC that tracks temperature variations. An ADC test chip is fabricated in 28-nm CMOS process and it demonstrates IMD3 <−89 dBc with two −9-dBFS tones at 180/190 MHz at room temperature, and 8 dB variation across −10 °C to 120 °C.

Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS

This paper presents an adaptive digital noise cancellation filter (DNCF) using cross-correlation (XCORR) developed for continuous-time (CT) multi-stage noise-shaping (MASH) ADCs. The XCORR engine continuously estimates the transfer functions of ΔΣ sub-loops and updates the coefficients for the DNCF. An ADC prototype with this engine is built in 28nm CMOS and it achieves 72dB of dynamic range over 440MHz BW, with a total power of 1.25W from 1V and 1.8 V supplies. Comparing to a power-up least-mean squares (LMS) engine, the XCORR-based adaptive DNCF achieves 2dB better noise cancellation across up to 10% supply variations.

Continuous-Time MASH Architectures forWideband DSMs

BW = f s/(2 OSR). As this equation indicates, wideband ΣΔ ADCs having bandwidths in the hundreds of MHz require clock frequencies in the GHz range even to obtain a relatively low OSR of ten. In such low-OSR systems, MASH architectures achieve better power efficiency than traditional single-loop ΣΔ ADCs. Nanometer CMOS process technologies enable continuous-time ΣΔ ADCs operating at GHz clock frequencies. However, the combination of continuous-time and low-OSR at a GHz clock frequency presents new challenges. In this paper, ΣΔ ADCs including the traditional single-loop and MASH, are reviewed in the context of wideband wireless applications with out-of-band blockers. A unique circuit block in continuous-time MASH, a continuous-time residue generation circuit, is discussed in detail. Two wideband MASH implementations in a 28 nm CMOS process are compared and their properties and performances are discussed based on the architectural differences.