José B. Silva

Design-oriented estimation of thermal noise in switched-capacitor circuits

Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II-III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV-VI ). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter.

Theory and applications of incremental /spl Delta//spl Sigma/ converters

Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.

Low-distortion delta-sigma topologies for MASH architectures

This paper describes low-distortion delta-sigma topologies with significant system and circuit-level advantages over traditional delta-sigma topologies, especially for wideband (low oversampling ratio) applications. A comparison between traditional and low-distortion MASH topologies shows how the latter can achieve higher performance while requiring smaller silicon area and power consumption.

A switched-capacitor DAC with analog mismatch correction

This paper describes a background calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analog converter. It can be used alone or in combination with mismatch shaping to achieve very high accuracy and linearity combined with high speed.

Incremental Delta-Sigma Structures for DC Measurement: an Overview

In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (DeltaSigma) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described. Two different analyses of the first-order incremental converter are presented, and based on these results two extensions to higher-order modulators are proposed. Since line-frequency noise suppression is often important in measurement applications, modulators followed by sinck filters are also analyzed. Equations are derived for the estimation of the required number of cycles for a given resolution and architecture. Finally, the design and implementation of a third-order incremental converter with a fourth-order sine filter is briefly discussed

A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications

A switched-R-MOSFET-C filter with tunable corner frequency is described. The tunability is achieved by varying the clock duty cycle using an automatic tuning circuit. This tuning method does not involve a change in any gate voltage, and is therefore particularly suitable for low-voltage and high-linearity applications. The advantages of the proposed method are illustrated with the design and simulation of a high-Q biquad filter.

Digital techniques for improved /spl Delta//spl Sigma/ data conversion

Two digital techniques are described in this tutorial, both aimed at improving the accuracy of delta-sigma data converters. The first one corrects adaptively for mismatch errors in a MASH ADC, while the other acquires and then corrects for the nonlinearity of the internal multibit DAC used in the ADC.

15.5 A 930mW 69dB-DR 465MHz-BW CT 1–2 MASH ADC in 28nm CMOS

The width of RF bands commonly used for cellular telecommunications has grown from 35-to-75MHz for 2G/3G/4G platforms to 100-to-200MHz for todays LTE, and the desire for relaxed image-rejection filtering has pushed the direct IF sampling frequencies to 300+ MHz. This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC IC that achieves 69dB of DR over a 465MHz signal bandwidth with a combined power consumption of 930mW from ±1.0V/1.8V supplies. The ADC IC is implemented in 28nm CMOS and achieves a peak SNDR of 65dB, a small-signal noise-spectral density (NSD) of -156dBFS/Hz, and a figure-of-merit (FOM) of 156dB over a signal bandwidth of 465MHz.

Design theory for high-order incremental converters

A/D converters used in instrumentation and measurements often require high absolute accuracy, including high linearity and negligible DC offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has all the advantages of the /spl Delta//spl Sigma/ (Delta-Sigma) converter, yet is capable of offset-free and accurate conversion. In this conference paper, theoretical and practical aspects of higher-order incremental converters are discussed. Operating principles, topologies and specialized digital filter design methods are addressed. The theoretical results are verified by showing design examples and simulation results.

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology

Software defined radios and wideband instrumentation demand the ability to digitize wide BW RF signals with moderately high dynamic range. A 12b 10GS/s ADC with an input analog bandwidth of 7.4GHz is developed for such applications in 28nm CMOS. The ADC achieves an SNR of 56dB, SNDR of 55dB and SFDR of 64dB with a 4GHz input at 10GS/s, and realizes an NSD of −157dBFS/Hz (i.e. DR = 60dB) while dissipating 2.9W.