Jian-Ming Wu

Two CMOS Dual-Feedback Common-Gate Low-Noise Amplifiers With Wideband Input and Noise Matching

This paper presents two CMOS common-gate (CG) low-noise amplifiers (LNAs) using different dual-feedback techniques, significantly reducing noise figure (NF) to around 2 dB over a wide frequency range. The proposed first CG LNA uses gm-boosted feedback and shunt-series transformer feedback to relieve the tradeoff between input and noise matching. The proposed second CG LNA further extends the input matching bandwidth by using gm-boosted feedback and shunt-shunt transformer feedback. Moreover, the transformer used for feedback in both CG LNAs causes gain peaking and thus a considerable increase of 3-dB gain bandwidth. After implementation in a 0.18- μm CMOS process, the first and second CG LNAs achieve an NF of 1.9-2.6 dB over a 3-dB gain bandwidth of 7 and 10 GHz, respectively. The comparison between simulated and measured results shows a good agreement.

Wideband common-gate low-noise amplifier with dual-feedback for simultaneous input and noise matching

This work designs and implements a wideband common-gate (CG) low-noise amplifier (LNA) with dual-feedback using 0.18 µm CMOS technology. The design is based on a mechanism of dual-feedback, which is composed of a transformer and a gm-boosting feedback, to overcome the trade-off between noise and input matching in common-gate topology without consuming additional dc power. Simultaneously, the noise figure and power gain are improved. The implemented wideband CG LNA achieves an S11 of below −10 dB, a NF of 1.9 – 2.65 dB, a power gain of 13.5 – 16.5 dB, and an IIP3 of −2 – 3 dBm, with a 3 dB gain bandwidth of 1 – 8 GHz; the chip consumes 10.8 mW.

A high IIP2 Gilbert mixer-based downconverter design for direct-conversion WiMAX receivers

A 2.6 GHz Gilbert mixer-based downconverter RFIC is designed and implemented in a 0.15 µm InGaAs pseudomorphic high electron mobility transistor (pHEMT) foundry process. A crucial goal for the design is to achieve high input second-order intercept point (IIP2) that is required in a direct-conversion WiMAX receiver. The adaptive biasing at the switching stage of this downconverter is used to compensate the unbalance of the input LO signals for improving the IIP2. The technique presented here enhances the IIP2 by 18.8 dBm without at the expense of reducing the conversion gain.

A sub-mW CMOS LNA for WSN applications

A sub-mW low-noise amplifier (LNA) is designed and implemented using a 0.18 μm CMOS standard process for wireless sensor network (WSN) applications. An important goal of the design is to achieve the low noise figure (NF) that is required in WSN receivers with low power consumption (PDC). The forward body bias technique is used to reduce power consumption of the LNA. A supply voltage of 0.6 V is used with a power consumption of 0.84 mW. The LNA operated at 2.4 GHz achieves a NF of 2.88 dB and a gain of 10.1 dB.

Diagnosis of EMI to laptop WWAN device from TFT-LCD driver using non-contact measurement-based transfer function technique

This paper presents a novel non-contact measurement technique for electromagnetic interference (EMI) diagnosis. The proposed technique uses vector network analyzer with antenna and near-field probes to measure the transfer function for an EMI path without interrupting the operation of device under test. As an example, with the help of the measured transfer function and equivalent source in the proposed technique, the EMI to laptop wireless wide area network (WWAN) device caused by a thin film transistor-liquid crystal display (TFT-LCD) driver is accurately diagnosed and appropriately treated. In addition, an easy-to-follow procedure is given for applying the presented non-contact measurement technique to the demonstrated example.

Low Power FSK Receiver Using an Oscillator-Based Injection-Locked Frequency Divider

This letter presents a novel frequency-shift keying (FSK) receiver using an oscillator-based injection-locked frequency divider (ILFD), thereby achieving high sensitivity, low dc-offset, and low power consumption. The proposed receiver comprises a low-noise amplifier, a divide-by-2 ring-oscillator-based ILFD, and a subharmonic mixer. Moreover, the proposed receiver is fabricated using 0.18 μm CMOS process and consumes 1.1 mW. Measurement results demonstrate that the proposed receiver has a sensitivity of -83 dBm at 10-3 bit error rate with 1 Mb/s data rate in receiving a 2.4 GHz Gaussian FSK signal.

A variable gain low-noise amplifier with noise and nonlinearity cancellation for DVB applications

A variable gain low-noise amplifier (LNA) RFIC with noise and nonlinearity cancellation is developed in 0.18-µm CMOS technology. This variable gain LNA is designed for the need of low power consumption and high performance in DVB applications. The variable gain LNA achieves the maximum gain of 9.2 – 14.4 dB from 50 MHz to 860 MHz, which also provides the dynamic range more than 30 dB. The input and output return losses less than −5.6 dB and −10 dB, respectively. The supply voltage is 1.8 V and power consumption is 19.8 mW. With the success of cancellation, the variable gain LNA with maximum gain has the measured noise figure of 2.5 – 3.5 dB and the measured OIP3 of 10 – 17 dBm from 50 MHz to 860 MHz. The chip area of the implemented variable gain LNA RFIC is 0.78 × 0.85 mm2.

Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices

This paper presents a stacked RF front-end (RFE) package for wideband receiver applications. While having a power consumption of 18 mW, the flipped CMOS chip consisting of a low-noise amplifier and a quadrature down-conversion mixer stacks on a glass integrated passive device (GIPD) substrate, subsequently achieving a noise figure of 2.2-2.8 dB and a conversion gain of 23-25 dB over 1-6 GHz. Moreover, the RFE package uses a GIPD balun with a high common-mode rejection ratio and a post-distortion linearizer in the CMOS mixer, subsequently resulting in an IIP2 of 57-68 dBm and an IIP3 of -5.2- -3.5 dBm over the entire operating band. This paper also elucidates how coupling between the flipped CMOS chip and GIPD balun affects the RFE linearity. Fabricated with 0.18-μm CMOS technology, the flipped CMOS chip is packaged on the GIPD substrate with a footprint area of 1.8×1.8 mm2.

Highly sensitive and low power injection-locked FSK receiver for short-range wireless applications

A highly sensitive frequency-shift keying (FSK) receiver with low power consumption that is based on the injection-locking technique is proposed for short-range wireless (SRW) applications. The proposed FSK receiver comprising a sub-mW low-noise amplifier (LNA), a trifilar transformer splitter, and an injection-locked self-oscillating mixer (SOM) is fabricated using 90 nm CMOS technology. Measurement results indicate a sensitivity of -81 dBm with a power consumption of 1.8 mW when a Bluetooth Gaussian frequency-shift keying (GFSK) modulated signal with a data rate of 1 Mb/s is received.

Ultralow Power Injection-Locked GFSK Receiver for Short-Range Wireless Systems

This brief presents a novel CMOS Gaussian frequency-shift keying (GFSK) receiver with an ultralow power consumption, which is based on the injection-locking technique for short-range wireless systems. Additionally, through reducing the oscillation current amplitude of the injection-locked oscillator, the GFSK receiver sensitivity is significantly improved. While comprising a submilliwatt low-noise amplifier, a trifilar transformer splitter, and an injection-locked self-oscillating mixer, the proposed receiver is fabricated using a 90-nm CMOS 1P9M technology. Measurement results indicate a sensitivity of -81 dBm, with a power consumption of 1.8 mW, when a Bluetooth GFSK signal with a data rate of 1 Mb/s is received.