Kuan-Chung Lu

Vertical interconnect measurement techniques based on double-sided probing system and short-open-load-reciprocal calibration

This work develops a double-sided probing system and calibration method for measuring the S-parameters of vertical interconnects at the wafer, package and socket level. The applicable device under test (DUTs) include through silicon vias (TSVs), plated through holes (PTHs), pogo pins and pressure sensitive conductive rubbers (PCRs). The effects of solder bumps and balls can also be taken into account. A short-open-load-reciprocal (SOLR) calibration method is used with a reciprocal thru to instead of the conventional short-open-load-thru (SOLT) which uses a standard thru. The S-parameters can be measured up to 40 GHz with a repeatable S21 parameter accuracy of better than 0.2 dB and 1 degree in magnitude and phase, respectively. Additionally, the eye diagrams are measured at a maximum data rate of 40 Gb/s and a minimum rise time of 10 ps with the help of Agilent physical layer test system (PLTS).

Scalable modeling and wideband measurement techniques for a signal TSV surrounded by multiple ground TSVs for RF/high-speed applications

The advantages of single-ended transmission lines are their simplicity and high flexibility of interconnection. Generally, shielding with additional ground lines is essential to improving the immunity of single-ended RF/high-speed signals against noise. However, this approach is very difficult to realize for a single-ended through silicon via (TSV) in 3D ICs because of the strong dependence of characteristic impedance on the number of ground TSVs. To address this issue, this work provides a physical and scalable equivalent-circuit model of a signal TSV that is circularly surrounded by multiple ground TSVs. Additionally, with the help of a double-sided probing system, wideband measurements of S-parameters of up to 40 GHz and eye-diagrams of 40 Gb/s signal are made to validate the modeled results.

Comparative Modeling of Single-Ended through-Silicon Vias in GS and GSG Configurations Up to V-Band Frequencies

This work presents a novel comparative modeling scheme for single-ended (SE) through-silicon vias (TSVs) in GSG and GS conflgurations. Physical scalable models based on the equations developed herein indicate that the use of two symmetric ground TSVs in GSG conflguration relatively increases the parasitic capacitance and conductance in the silicon substrate. However, this increase in the parasitic capacitance requires that the parasitic inductance of SE TSV is reduced to maintain the same phase velocity in silicon. According to the modeling results, the GSG conflguration has a larger insertion loss than that of the GS conflguration because the former has a higher substrate conductance. Nevertheless, when measured using RF coaxial probes, the GSG conflguration exhibits a larger measurement bandwidth than the GS conflguration. Finally, with the assistance of a double-sided probing system, wideband S-parameter measurement can validate the established equivalent-circuit model of SE TSV in GSG conflguration up to V-band frequencies.

Ultralow Phase Noise and Wideband CMOS VCO Using Symmetrical Body-Bias PMOS Varactors

This letter presents an ultralow phase-noise and wide turning-range CMOS voltage-controlled oscillator (VCO) for 5 GHz WLAN applications. The proposed PMOS-only VCO design with body-bias varactors achieves a tuning range of 20.4% and a phase noise of -138.4 dBc/Hz at 1 MHz offset. The total power consumption of the VCO core is 13.1 mW using a 1.8 V supply voltage. The achieved figure of merit with tuning range (FOMT) is -207.2 for the proposed CMOS VCO.

Packaging effects on a CMOS low-noise amplifier: Flip-chip versus wirebond

A model-based study is presented to compare the effects between flip-chip and wirebond package on a low-noise amplifier (LNA) in a 2.4 GHz CMOS wireless local area network (WLAN) receiver. To construct the package electrical models, specific modeling dies are designed to help extract the equivalent-circuit parameters from measured S-parameters for chip-package interconnects. Furthermore, the ground proximity effects on on-chip spiral inductors in a flip-chip package are also modeled in this study. Excellent agreement between modeling and measurement is obtained up to 20 GHz for a 64-pin flip-chip ball grid array (FCBGA) package and a 64-pin wirebond quad flat nonlead (QFN) package. In practical applications, the established package models are used to predict the RF specifications of a 2.4 GHz CMOS LNA when packaged in the above two packages. Consequently, chip-package co-simulation achieves a good agreement with measurement, and thus can persuasively account for the effects caused by the two different packages.

Wideband and scalable equivalent-circuit model for differential through silicon vias with measurement verification

The three-dimensional integrated circuit has attracted much attention because of evolving functions in todays integrated circuit products and continuing demands for low power consumption and miniature chip size. Through silicon vias (TSVs) provide a vertical interconnection between stacked dies with much shorter and denser connectivity than the hybrid horizontal and bondwire interconnects in conventional use. Moreover, a differential interconnect is more commonly used in high-speed digital circuits for its higher immunity to common-mode noise than a single-ended one. Therefore, a scalable physical model for differential TSVs has been proposed in this work. Consequently, the mixed-mode S-parameters were generated from the established model to compare electrical performance between a GSSG- and GSGSG-type differential TSV. Additionally, with the help of a double-sided probing system, four-port S-parameters were measured up to 40 GHz to validate the modeled results.

Comparative modeling study of single-ended through-silicon via between the G-S and G-S-G configuration

This paper presents a comparative modeling of single-ended (SE) through silicon via (TSV) between the G-S and G-S-G configuration. The simulation based on a 3D quasi-static field solver indicates that the use of two ground TSVs produces greater parasitic capacitance and conductance in the silicon substrate. However, because of the increase of the parasitic capacitance, the parasitic inductance of the SE TSV is reduced to maintain the same phase velocity in silicon. According to the modeled results, the G-S-G configuration has a larger insertion loss due to a higher substrate conductance when compared to the G-S configuration. Nonetheless, when measured with the coaxial probes, the G-S-G configuration exhibits a larger measurement bandwidth than the G-S configuration. Finally, wideband S-parameter measurements with the help of a double-sided probing system can validate the modeled results at frequencies up to 50 GHz in the G-S-G configuration.

A variable gain low-noise amplifier with noise and nonlinearity cancellation for DVB applications

A variable gain low-noise amplifier (LNA) RFIC with noise and nonlinearity cancellation is developed in 0.18-µm CMOS technology. This variable gain LNA is designed for the need of low power consumption and high performance in DVB applications. The variable gain LNA achieves the maximum gain of 9.2 – 14.4 dB from 50 MHz to 860 MHz, which also provides the dynamic range more than 30 dB. The input and output return losses less than −5.6 dB and −10 dB, respectively. The supply voltage is 1.8 V and power consumption is 19.8 mW. With the success of cancellation, the variable gain LNA with maximum gain has the measured noise figure of 2.5 – 3.5 dB and the measured OIP3 of 10 – 17 dBm from 50 MHz to 860 MHz. The chip area of the implemented variable gain LNA RFIC is 0.78 × 0.85 mm2.

Scalable modeling of Through Silicon Vias up to milimeter-wave frequency

In this study, measurements are made to validate the electrical performance of a Through Silicon Via (TSV) interconnection up to 40GHz, and the results of the wideband scalable model of TSV is proposed and compared with the measured data. Measurement of the TSV structure demonstrates its advantages of low parasitic capacitance and low insertion loss at high frequency.

Analytical modeling of vertical interconnect in single-ended applications

Despite the shorter physical length and superior electrical properties of the vertical interconnects, the arrangement of corresponding grounding pins drastically affects the characteristic impedance, resulting in impedance mismatch during the propagation of signals, which leads to signal reflection. Therefore, to potentially overcome this disadvantage, this paper endeavors to establish the analytical model of the vertical interconnects for improving the impedance matching in single-ended configurations. The key approach is to use the method of image charges for analyzing the capacitance between the signal pin and grounding pins of the vertical interconnect. The established models are capable of predicting the changes in the capacitance of various grounding pin arrangements in the vertical interconnect, and based on the prediction results the optimal impedance-matching design can be found.