Fu-Yi Han

A Rigorous Study of Package and PCB Effects on W-CDMA Upconverter RFICs

A Volterra-series analysis is presented to study the package and printed circuit board (PCB) effects on the linearity of two wideband code-division multiple-access upconverter RF integrated circuit (RFIC) designs. The first design adopts a recently popular micromixer with a class AB input stage. The second design is based on a commonly used Gilbert mixer with emitter degeneration. Both upconverter RFICs are designed to have the same adjacent channel power ratio (ACPR) in the chip-level simulation. After fabrication, packaging, and testing on the PCB, the micromixer-based design consumes less direct current, but causes more degradation in the ACPR performance due to the influence of package and PCB when compared to the Gilbert mixer-based design. The theoretical analysis indicates that the micromixer-based upconverter RFIC is rather susceptible to the parasitic effects from the ground interconnect and, therefore, it needs a better package solution with a lower ground inductance for practical use. Comparison between theory and measurement shows good agreement in predicting the variations of conversion gain and ACPR due to the presence of the package and PCB

Direct-conversion quadrature modulator MMIC design with a new 90/spl deg/ phase shifter including package and PCB effects for W-CDMA applications

This paper presents a wideband code-division multiple-access direct-conversion quadrature modulator monolithic-microwave integrated-circuit (MMIC) design that employs a new technique to generate the 90deg phase shift with low implementation loss. From the bare-chip measurement, this new 90deg phase shifter has been proven with an amplitude and phase error less than 0.6 dB and 0.8deg, respectively, within the applied frequency range from 1.85 to 1.98 GHz. The package and printed circuit board (PCB) interconnects are also analyzed using the three-dimensional electromagnetic simulation tool and transformed into the equivalent-circuit elements for co-simulation with the designed quadrature modulator MMIC. The degradation of error vector magnitude and sideband suppression due to the package and PCB can be well predicted and verified by measurements. Although the proposed 90deg phase shifter has a remarkable advantage over the others in implementation loss, it is quite susceptible to the package and PCB effects and needs more design efforts to deal with those effects

Packaging effects on a CMOS low-noise amplifier: Flip-chip versus wirebond

A model-based study is presented to compare the effects between flip-chip and wirebond package on a low-noise amplifier (LNA) in a 2.4 GHz CMOS wireless local area network (WLAN) receiver. To construct the package electrical models, specific modeling dies are designed to help extract the equivalent-circuit parameters from measured S-parameters for chip-package interconnects. Furthermore, the ground proximity effects on on-chip spiral inductors in a flip-chip package are also modeled in this study. Excellent agreement between modeling and measurement is obtained up to 20 GHz for a 64-pin flip-chip ball grid array (FCBGA) package and a 64-pin wirebond quad flat nonlead (QFN) package. In practical applications, the established package models are used to predict the RF specifications of a 2.4 GHz CMOS LNA when packaged in the above two packages. Consequently, chip-package co-simulation achieves a good agreement with measurement, and thus can persuasively account for the effects caused by the two different packages.

Direct-conversion quadrature modulator MMIC design with a new 90 degrees phase shifter including package and PCB effects for W-CDMA applications

A 1.9 GHz GaAs direct-conversion quadrature modulator MMIC adopting a new technique to generate 90/spl deg/; phase shift for W-CDMA applications is presented. This 90/spl deg/ phase shifter achieves a phase error less than 1.5/spl deg/ from 1.8 GHz to 2 GHz with extremely low implementation loss. The package and PCB interconnects are also analyzed using the 3-D EM simulation tool and transformed into the equivalent-circuit elements for co-simulation with the designed modulator MMIC. The dominant package and PCB effect is to degrade the sideband suppression, which is disadvantageous to the modulation quality.

A rigorous study of package and PCB effects on W-CDMA RFICs

This paper presents a practical evaluation method for package and PCB effects on RFICs in W-CDMA applications. The package and PCB interconnects are characterized rigorously by establishing their equivalent parasitic circuits with the help of the 3-D EM-simulation tool. For demonstration, two 1.9 GHz RFICs were fabricated by a GaAs HBT foundry process, and then housed in the leadless wirebond packages, and finally surface-mounted onto PCBs for testing. With the established equivalent parasite circuits, the package and PCB effects can be included in the RFIC simulation in the design stage. The simulated results agree quite well with the final measured results.

Packaging effects on the figure of merit of a CMOS cascode low-noise amplifier: Flip-chip versus wire-bond

A comprehensive study is presented to compare the effects between flip-chip and wire-bond packages on a front-end cascode low-noise amplifier (LNA) in a 2.4 GHz CMOS wireless local area network (WLAN) receiver. To construct the package electrical models, specific modeling dies are designed to help extract the equivalent-circuit elements from measured S-parameters for chip-package interconnects. Furthermore, the ground-proximity effect on on-chip spiral inductors in a flip-chip package is presented for the first time in this modeling study. For practical applications, the established package models are used in a chip-package co-simulation to predict the degradation of figure of merit for the cascode LNA under packaged condition.

Chip-Package-Board Codesign of Highly Linear 3G-CDMA Upconverter Modules

This paper presents a practical example of chip-packageboard codesign for a highly linear 3G-CDMA upconverter module. A 1.9 GHz upconverter MMIC is designed and implemented using InGaAs HBT foundry process. The goal for this MMIC design is to achieve the high linearity required in a W-CDMA system. In addition, the complete interconnect effects of package and PCB are considered rigorously by establishing their equivalent circuits with the help of the EDA EM-simulation tool. The proposed design for the upconverter MMIC adopts a Gilbert-cell mixer with emitter-degeneration to enhance the linearity performance. This MMIC is housed in a leadless 24-pin BCC package and surface-mounted onto an FR4 PCB for measuring the complete RF parameters. The simulation results from both the theoretical approach and the EDA circuit-simulation tool for this upconverter module agree quite well with the final measurement results.

Implementation of a W-CDMA direct-conversion IQ modulator module including evaluation of chip-package-board interactions

This paper presents a W-CDMA direct-conversion IQ modulator MMIC design that employs a new technique to generate the 90deg phase shift with low implementation loss. The package and PCB effects on the implemented IQ modulator MMIC when further developed as a board module are studied. The package and PCB interconnects are analyzed using the 3-D EM simulation tool and transformed into the equivalent-circuit elements for co-simulation with the IQ modulator MMIC. The degradation of error vector magnitude and sideband suppression due to the presence of package and PCB can be well predicted by the co-simulation results and then verified by the final measurement results

Comparing flip-chip and wire-bond package effects on a receiver low-noise amplifier

A comprehensive study based on chip-package co-modeling compares the effects between flip-chip ball-grid-array (FC-BGA) and wire-bond quad-flat-nonlead (WB-QFN) packages on a front-end cascode low-noise amplifier (LNA) in a 2.45 GHz CMOS wireless local area network (WLAN) receiver. In practical applications, the established package models are used to predict the degradation of figure of merit (FOM) for the cascode LNA under packaged condition. Chip-package co-modeling results achieve good agreement with measurements, and thus can persuasively account for the complete effects caused by the two different packages on the cascode LNA.

A dual-conversion zero-IF design for DVB-H RF tuner applications

This paper presents the RFIC design that uses TSMC 0.18µm CMOS process to implement a DVB-H RF tuner. The design is based on a dual-conversion zero-IF architecture. Compared to the conventional up-down architecture, this adopted architecture has the advantages of no IF SAW filter but still can easily reject the image signal. To pass the protection-ratio specification, the most challenging one in DVB-H tuner specifications, this RFIC design is featured with a broadband LNA with a variable gain, a highly linear up-converting mixer with a double-balanced resistive FET architecture, and a high-linearity quadrature demodulator with the transconductance linearization technique. The important CW measured results is summarized as follows: The DC power consumption is 70.2 mW. From 50 to 860 MHz, the maximum gain varies from 19.7 to 29.2 dB with an adjustable attenuation more than 50 dB. Under the maximum-gain condition, the noise figure varies from 4.6 to 12 dB, and the OIP3 varies from 0.1 to 2.2 dBm. The CW test results agree quite well with the link-budget analysis results.