Jianchao Lu

Clock mesh synthesis with gated local trees and activity driven register clustering

A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in the design. This is the first work known in literature that encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. Experimental results show that with gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The proposed method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

Clock buffer polarity assignment considering capacitive load

A clock buffer polarity assignment method is proposed that considers the impact of capacitive load on the peak current. It is shown that the peak current on the supply rails of a buffer is a monotonically increasing function of its driving capacitance. Consequently, the polarity of a clock buffer is assigned based on its capacitive load. The proposed method can be applied to assign buffer polarity on any number of levels of the clock tree. In experiments, the peak current on the clock tree in each local area is reduced by 36.3% on average. The worse case peak current of all the local areas are reduced by 35.7% on average. The proposed method is implemented with a pseudo-polynomial dynamic programming scheme demonstrating runtimes under a minute.

Integrated Clock Mesh Synthesis With Incremental Register Placement

A clock mesh planning and synthesis method is proposed which significantly reduces the power dissipation on the network while considering the power density and timing slack simultaneously. The proposed method is performed at the postplacement stage and consists of three major steps: 1) feasible moving region construction of each register considering timing slack; 2) mesh grid wire generation and placement; and 3) incremental register placement for stub wire minimization considering power density and timing slack. The advantages of the proposed method are the reduced power dissipation-28% on average on the benchmark circuits-the optimized power density, and the guaranteed nonnegative timing slack. These advantages are possible through a decreased timing slack (1.1% of the clock period) and change in the logic wirelength (+5.9%) on the benchmark circuits.

Steiner tree based rotary clock routing with bounded skew and capacitive load balancing

A novel rotary clock network routing method is proposed for the low-power resonant rotary clocking technology which guarantees: 1. The balanced capacitive load driven by each of the tapping points on the rotary rings, 2. Customized bounded clock skew among all the registers on chip, 3. A sub-optimally minimized total wirelength of the clock wire routes. In the proposed method, a forest of steiner trees is first created which connects the registers so as to achieve zero skew and greedily balance the total capacitance of each tree. Then, a balanced assignment of the steiner trees to the tapping points is performed to guarantee a balanced capacitive load on the rotary network. The proposed routing method is tested with the ISPD clock network contest and IBM r1–r5 benchmarks. The experimental results show that the capacitive load imbalance is very limited. The total wirelength is reduced by 64.2% compared to the best previous work known in literature through the combination of steiner tree routing and the assignment of trees to the tapping points. The average clock skew simulated using HSPICE is only 8.8ps when the bounded skew target is set to 10.0ps.

Clock Tree Synthesis with XOR Gates for Polarity Assignment

A novel clock tree synthesis (CTS) method is proposed that improves the reliability of an integrated circuit system through reducing the peak current on the power/ground rails drawn by the clock tree buffers. The proposed CTS method entails the integration of XOR gates at one level of the clock tree to enable polarity assignment for peak current reduction. Unlike previous polarity assignment methods, the skew of the generated clock tree with XORs is preserved as the physical layout of the clock tree is preserved during the polarity assignment process. Furthermore, the proposed clock tree permits the implementation of most of the previous polarity assignment methods through configurability of the control input of the XOR gates. Experimental results show that the peak current on the power/ground rails of the clock tree is reduced by an average of 55.2% without any degradation in the original clock skew.

From RTL to GDSII: An ASIC design course development using Synopsys® University Program

The development of an ASIC design course using the Synopsys® University Program lectures, labs and tools is presented in this paper. The ASIC design course lasts for 20 weeks and the students learn the design flow using tools including Design Compiler™, IC Compiler™ and PrimeTime™. The syllabus is developed based on the Synopsys® University Program Curriculum. Besides the curriculum, the students are assigned projects to synthesize some small circuits to gain more in-depth knowledge about the ASIC design flow. A keystone project is assigned to facilitate the application of the entire IC physical design flow on an industrial size processor design.

Post-CTS clock skew scheduling with limited delay buffering

Proposed post-clock-tree-synthesis (CTS) optimization method is delay buffering at the leaves of the clock tree to implement a limited version of clock skew scheduling. The method suggests the limitation of delay buffering on each clock tree branch as well as a global monitoring of total amount of delay buffering to improve the circuit performance. The delay buffering for non-zero clock skew operation is performed only after the clock sinks in order to preserve the structure and the optimizations implemented with any clock tree synthesis methodology. Experimental results demonstrate the superiority of the proposed post-CTS methodology over previous methods and demonstrate an important trend of clock period improvement over varying upper bounds of delay buffering. It is shown that the majority of the clock period improvement achievable through clock skew scheduling is obtained through very limited buffering (≈43% average improvement through 10% of max buffering).

A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs

This paper presents a clock polarity assignment flow which permits post-silicon reconfigurability. The proposed method inserts xor gates at one level of the clock tree to facilitate the polarity assignment. The polarity of the xor gates can be reconfigured for different modes of clock gating (sleep mode, busy mode, etc.) such that a mode-specific reduction of the peak current can be achieved. Experimental results show that the worst case peak current on a clock tree can be reduced by 33.3% by assigning polarity to xor gates at the sink level of the clock tree. An additional 12.8% reduction in the worst case peak current can be achieved by reconfiguring the polarity assignment based on the clock gating information. The proposed flow increases the area by 7.1% but reduces both the total power consumption by 23.8% and the global skew increase (due to polarity assignment) from 19.3 to 8.8 ps. The insertion of xor gates at the non-sink nodes is also studied to further reduce the global skew increase and the area overhead.

Clock buffer polarity assignment with skew tuning

A clock polarity assignment method is proposed that reduces the peak current on the vdd/gnd rails of an integrated circuit. The impacts of (i) the output capacitive load on the peak current drawn by the sink-level clock buffers, and (ii) the buffer/inverter replacement scheme of polarity assignment on timing accuracy are considered in the formulation. The proposed sink-level-only polarity assignment is performed by a lexi-search algorithm in order to balance the peak current on the clock tree. Most of the previous polarity assignment methods that do not include clock tree resynthesis lead to an undesirable increase in the worst corner clock skew. Hence, a skew-tuning scheme is proposed that reduces the clock skew through polarity refinement and not through clock tree resynthesis. The proposed polarity assignment method with the skew-tuning scheme is implemented within an industrial design flow for practicality. Experimental results show that the worst-case peak current drawn by the clock tree can be reduced by an average of 36.5%. The worst corner clock skew is increased from 60.7ps to 76.2ps by applying the proposed polarity assignment method. The proposed skew-tuning scheme reduces the worst-case clock skew from 76.2ps to 61.5ps, on average, with a limited degradation in the peak current improvement (36.5% to 31.2%, on average).

Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis

A novel clock mesh network synthesis approach is proposed in this paper which generates an improved mesh size with registers placed incrementally considering the timing slack on the data paths and the non-uniform grid wire placement. The primary objective of the method is to reduce the power dissipation without a global skew degradation, which is achieved through a sparse and non-uniform mesh implementation with registers incrementally placed in close vicinity to the mesh grids. The incremental register placement is based on the timing information in order to preserve the timing slack of the circuit. Experimental results show that the total wirelength (mesh grid wires and stub wires) as well as the power dissipation is reduced significantly on the clock mesh network. Specifically, the wirelength of the mesh network and the power dissipation of the clock network are reduced by 52% and 48% on average, respectively. Moreover, the global clock skew and the non-negative timing slack are preserved.