Ying Teng

A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs

This paper presents a clock polarity assignment flow which permits post-silicon reconfigurability. The proposed method inserts xor gates at one level of the clock tree to facilitate the polarity assignment. The polarity of the xor gates can be reconfigured for different modes of clock gating (sleep mode, busy mode, etc.) such that a mode-specific reduction of the peak current can be achieved. Experimental results show that the worst case peak current on a clock tree can be reduced by 33.3% by assigning polarity to xor gates at the sink level of the clock tree. An additional 12.8% reduction in the worst case peak current can be achieved by reconfiguring the polarity assignment based on the clock gating information. The proposed flow increases the area by 7.1% but reduces both the total power consumption by 23.8% and the global skew increase (due to polarity assignment) from 19.3 to 8.8 ps. The insertion of xor gates at the non-sink nodes is also studied to further reduce the global skew increase and the area overhead.

Synchronization scheme for brick-based rotary oscillator arrays

In this paper, a brick-based rotary oscillator array (ROA) synchronization scheme is proposed, which directs all the rotary traveling wave oscillators (RTWOs) in the ROA to rotate in a pre-determined direction. This synchronization scheme increases the speed of the ROA synchronization process by eliminating the repetitive start-up trials due to start-ups from incorrect points on the oscillatory array. Simulation results confirm the effectiveness of the ROA synchronization scheme. Furthermore, the synchronization scheme is applied to an ROA-based clock generation and distribution network designed for an ISPD 10 clock benchmark in order to demonstrate its application at a larger scale.

ROA-brick topology for rotary resonant clocks

This paper presents a topology design-based solution that addresses one of the major challenges in the design of Rotary Traveling Wave Oscillator (RTWO) based clock networks—the direction of oscillation. A “rotary oscillator array (ROA) brick” structure is proposed that guarantees the consistency of the rotation direction of the traveling signals on all the RTWO rings in an ROA. The ROA built from ROA bricks has the following advantages: (1) The same phase point of all the RTWO rings in the array can easily be tracked, (2) The same phase points of the ROA are independent of the specific rotation direction of the traveling signals on the ROA. SPICE simulations demonstrate these advantages of the brick-based ROA circuit design in establishing the directional consistency of the RTWO rings.

Process variation sensitivity of the Rotary Traveling Wave Oscillator

Rotary clocking is a low-power technology for multi-GHz clock generation and distribution. In this paper, a sensitivity analysis of the Rotary Traveling Wave Oscillator (RTWO) to process variations is presented based on a 90 nm technology. The analysis is focused on the effects of 1) multiple process corners, 2) power supply fluctuation, 3) chip temperature change, 4) the variations of the RTWO transmission line width and separation, on the operating frequency and power consumption of the RTWO. The individual analysis of these factors is presented as well as a Monte-Carlo based analysis to analyze the comprehensive effects of the process parameter variations and process corners. SPICE simulation results show that the RTWO exhibits a natural robustness to resist these on-chip variations.

ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design

This paper presents a topology-based solution for a low-skew rotary oscillator array (ROA) clock distribution network design. An ROA-brick structure is proposed that limits the traveling wave oscillation to only two uniform ring rotation directions in the ROA-brick: all the rings in clockwise (CW) direction or all the rings in counter CW direction. An ROA built from the ROA-bricks has the following advantages: 1) similar to the ROA-brick, only two uniform ring rotation directions are feasible in the ROA; 2) the same phase tapping points of all the rings in the ROA are identifiable; and 3) these same phase tapping points of the ROA are independent from the two possible rotation directions. It is mathematically proved that the ROA-brick is the only ROA structure, which can limit the ring rotation direction combinations so as to guarantee the generation of same phase clock signals. The proposed brick-based ROA clock generation and distribution networks are designed for ISPD 10 clock benchmarks demonstrating the gigahertz operation with the low-skew clock generation and distributions through HSPICE.

Sparse-rotary oscillator array (SROA) design for power and skew reduction

This paper presents a unique rotary oscillator array (ROA) topology—the sparse-ROA (SROA). The SROA eliminates the need for redundant rings in a typical, mesh-like rotary topology optimizing the global distribution network of the resonant clocking technology. To this end, a design methodology is proposed for SROA construction based on the distribution of the synchronous components. The methodology eliminates the redundant rings of the ROA and reduces the tapping wirelength, which leads to a power saving of 32.1%. Furthermore, a skew control function is implemented into the SROA design methodology as a part of the optimization of the connections among tapping points and subtree roots. This control function leads to a clock skew reduction of 47.1% compared to a square-shaped ROA network design, which is verified through HSPICE.

Frequency-centric resonant rotary clock distribution network design

A frequency-centric methodology is proposed for the selection of the physical parameters of the resonant rotary clock for a target frequency. This proposed methodology is performed once for each target frequency on a semiconductor technology, in order to create a cell library of resonant rotary clock design components. A case study is performed to demonstrate the efficiency of the proposed methodology in accuracy and run-time. Simulation results show that the frequency-centric design provides a good approximation for the resonant clock distribution network. At target frequencies between 4GHz and 6GHz, the frequency difference is less than 0.20% and the run-time is reduced by approximately 70% compared to the traditional HSPICE simulation of an entire SROA network without the proposed simplifications for run-time improvement.

Resonant frequency divider design methodology for dynamic frequency scaling

A rotary traveling wave oscillator (RTWO) frequency divider design methodology is proposed for dynamic frequency scaling. The proposed methodology can be used for designing dividers for integer division ratios of 3 to 9 within one circuit topology. HSPICE-based experiments are performed to test the electrical characteristics of the RTWO frequency dividers. The simulation results show that the power consumption of a frequency divider is as low as approximately 5mW for different frequency division ratios.

Rotary traveling wave oscillator frequency division at nanoscale technologies

Resonant clocking is an alternative to the traditional clock generation and network design which provides a low power, low skew solution for clock generation and distribution [1, 2, 4, 6, 7]. Rotary traveling wave oscillator (RTWO) [7] based resonant clocking technology is a particularly promising approach, which provides high frequency oscillation signals with rail-to-rail signal amplitude and multiple clock phases. However, the cost of a resonant oscillator, such as the power consumption and area overhead, grow rapidly along with the decrease of the target resonant frequency. Due to this inability to down-scale the naturally high frequency of resonant clocks, their application at lower frequencies remains limited. For instance, the resonant clocking implementation on AMD Piledriver chip [5] is only used at high frequencies, and the clock network is multiplexed off to be driven by a non-resonant clock source for lower frequency modes. The only prior work on resonant clock frequency division is in a USPTO-filed patent [3]. The patent [3] describes a circuitry for frequency division of the RTWO-based resonant clocking that uses the “spot-advancing” blocks (SABs) driven by multi-phases of the rotary clock. The circuitry of the spot-advancing block (SAB) is shown in Fig. 1, which is the core cell in the RTWO frequency divider. The SAB is composed of 6 transistors. When operation starts, the SABs advance a 1 value pulse from left to right through the Spot in port to the Spot out port. Suppose Spot out1 of SAB1 becomes 1, a connection is built between Clk2 and Spot mid2 in SAB2. When Spot mid2 discharged to Clk2 and become 0, a path is formed between Clk2 and Spot out2 in SAB2 meanwhile the path between Clk1 and Spot out1 in SAB1 is closed. When the Spot out2 of SAB2 becomes 1, it drives the Spot out1 of SAB1 (which is also