Jiang-Hung Chen

Electrical and microstructural characteristics of Ti contacts on (001)Si

An investigation of the electrical and microstructural characteristics of the Ti contact on silicon has been carried out. The presence of As in Ti/n+-Si samples was found to retard the formation of polycrystalline silicide (p-silicide) compared with that in Ti/p+-Si samples with BF2+ implantation. Amorphous interlayers (a-interlayers) were found to be present in both Ti/n-Si and Ti/p-Si samples annealed at temperatures of and lower than 450u2009°C. Although the Schottky barrier heights (SBH’s) vary for about 0.05–0.08 eV for samples annealed over a temperature range from room temperature to 900u2009°C, SBH’s at the a-interlayer/n-Si and a-interlayer/p-Si were measured to be about 0.52–0.54 and 0.59–0.57 eV, respectively. The specific contact resistance (ρc) in the Ti/n+-Si system was measured to be the lowest with a value of 1.4×10−7 Ωu2009cm2 when the a interlayer is present. In Ti/p+-Si system, the minimum ρc is about 3×10−7 Ωu2009cm2. The variation in contact resistance with annealing temperature for both Ti/n+-Si and...

Poly-Si Nanowire Nonvolatile Memory With Nanocrystal Indium–Gallium–Zinc–Oxide Charge-Trapping Layer

This letter introduces a polycrystalline silicon (poly-Si) thin-film nonvolatile memory (NVM) with a nanocrystal (NC) indium-gallium-zinc-oxide (IGZO) charge-trapping layer. Experimental results indicate that this NVM exhibits high and symmetric program/erase speeds through the Fowler-Nordheim tunneling mechanism. The memory window loss of the NVM with NC IGZO charge-trapping layer is 25% after 104 s at 85°C due to deep quantum well, as well as high-density and deep trap sites in NC IGZO charge-trapping layer. Accordingly, a poly-Si thin-film transistor with NC IGZO charge-trapping layer is promising for NVM applications.

2-bit operation based on modulated Fowler-Nordheim tunneling in charge-trapping flash memory cell

This work proposes a spatially charge tunneling method for program/erase (P/E) based on the drain-modulated Fowler-Nordheim (MFN) tunneling in a polycrystalline silicon channel charge-trap type flash memory device. The program mechanism and the simulation of the MFN are discussed. 2-bit operations based on MFN and channel hot electron injection were demonstrated. MFN 2-bit operation and conventional 2-bit operation present different transfer curves, indicating that charge is injected into the different regions. The MFN P/E operation provides flexibility in flash memory applications.

Interfacial reactions of titanium thin films on ion implanted (001) Si

Abstract An investigation on the influences of doping impurities on the formation of titanium silicide has been carried out. The formation of polycrystalline silicide was observed to be retarded by the presence of As in Ti As + −Si samples compared with those in Ti BF 2 + − Si samples. Superior thermal stability of TiSi 2 was found to occur in BF 2 + implanted samples than that in blank and As + implanted samples. The resistance to island formation in BF 2 + implanted samples is attributed to the retardation of grain growth by the segregation of fluorine atoms at the grain boundaries.

Schottky barrier heights of the amorphous interlayer/Si interfaces in titanium thin films on (001)Si

Schottky barrier heights (SBHs) of amorphous interlayer/Si interfaces in Ti thin films on (001)Si have been measured by forward current‐voltage technique. A‐interlayers were observed to form by cross‐sectional transmission electron microscopy in both Ti thin films on n‐ and p‐type silicon systems in samples annealed at temperatures of and lower than 450u2009°C for 30 s. Although the SBHs vary for about 0.05–0.08 eV for samples annealed over a temperature range from room temperature to 900u2009°C, SBHs at the a‐interlayer/n‐Si and a‐interlayer/p‐Si were measured to be 0.52–0.54 and 0.59–0.57 eV, respectively. Formation of homogeneous metal a‐interlayer/Si interfaces correlated with their SBHs in a number of refractory metal‐silicon systems promises to greatly clarify the SBH formation mechanisms.

Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory

This work demonstrates a dual-pi-gate TaN–Al2O3–Si3N4–SiO2–silicon (TANOS) flash memory with nanowires (NWs) channel. Simulation under modulated Fowler–Nordheim (MFN) tunneling indicates that the source-side tunneling oxide of the dual-gate (DG) TANOS NVM has an electric field larger than 6 MV/cm. A novel 2-bit operation of DG TANOS NVM can thus be performed by MFN programming and band-to-band tunneling-induced hot–hole injection (BTBTHHI) erasing. Additionally, the DG TANOS memory shows better program/erase characteristics and clearer distinguishability than a single-gate (SG) device under 2-bit operation. In reliability results, the DG TANOS memory shows better retention and endurance than the SG device.

Thermal stability of TiSi2 on ion implanted silicon

Abstract Thermal stability of TiSi 2 on blank, high-dose BF 2 + -, B + -, As + -, and P + -implanted silicon has been investigated by both cross-sectional and plan view transmission electron microscopy as well as by sheet resistance measurements. The surface morphology of TiSi 2 was found to be significantly influenced by the implantation in silicon substrate. Simultaneous presence of B and F was found to be most effective in retarding the degradation of surface morphology of the TiSi 2 thin films. Sheet resistance data were found to correlate well with the morphological and microstructural observation. The mechanism for the stabilization of silicide films are discussed.

Polycrystalline-Si TFT TANOS Flash Memory Cell With Si Nanocrystals for High Program/Erase Speed and Good Retention

This letter presents a polycrystalline-silicon channel TaN-Al2O3-Si3N4-SiO2-silicon (TANOS) nonvolatile memory (NVM) with a charge-trapping layer of embedded Si nanocrystals (NCs) (Si-NCs). The fabrication process of the Si-NCs is simple and highly compatible with the current Flash process. NCs enhance the program/erase speed of the NVM devices because the interface between Si-NCs and nitride contains numerous trapping sites for storing electrons. Moreover, the Si-NCs locally concentrate the electric field and reduce the effective nitride thickness. The NC TANOS exhibits a charge loss of only 5% for ten years of data storage.

Π-gate nanowires TANOS poly-Si TFT nonvolatile memory

This work we demonstrate a TANOS nonvolatile memory (NVM) with poly-Si nanowire (NW) channels and Pi-gate (Π-gate) structure. Π-gate structure in this TANOS NVM increase on current (I<inf>on</inf>), decrease threshold voltage (V<inf>th</inf>) and subthreshold slope (SS), and enlarge the memory window (ΔV<inf>th</inf>). This NVM device behaves fast program/erase (P/E) speed; 3 V memory window can be achieved by applying 18 V in 10 µs. The 70 % of initial memory window has been maintained after 10⁴ P/E-cycle stress.