Water Lur

Bond‐structure changes of liquid phase deposited oxide (SiO2−xFx) on N2 annealing

Fluorine can be naturally incorporated into the silicon oxide (SiO2−xFx) prepared by the liquid phase deposition (LPD) method at 35 °C. Fourier transform infrared and x‐ray photoelectron spectroscopy spectra show that an annealing treatment can change its bond‐structure. Changes in properties accompanying the restructuring are also observed. The annealing also densifies the LPD oxide and reduces its thickness because Si–F intensity decreases and the Si–O–Si intensity increases as annealing temperature increases.

A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing

A 0.25 /spl mu/m CMOS technology, with 6 layers of fully planarized interconnect, has been developed for versatile, flexible, and fast turn-around foundry manufacturing. A 0.6 /spl mu/m layout pitch has been successfully demonstrated for active, gate poly, and first metal layers. The 0.25 /spl mu/m, 50 A Tox and the 0.35 /spl mu/m, 65 A Tox devices were designed to support the 2.5 V core and the 3.3 V I/O circuits respectively on the same chip. In addition, high-performance 0.18 /spl mu/m, 40 A Tox transistors are also available for low-power applications at 1.8 V Vcc. Gate-delay is 40 p-sec at 2.5 V for the 0.25 /spl mu/m device, and 35 p-sec at 1.8 V for the 0.18 /spl mu/m device. The embedded 6 T SRAM cell size is 6.34 /spl mu/m/sup 2/. Considerations in process architecture and device design, relevant to foundry manufacturing, are also addressed on this 6-level-metal 0.25 /spl mu/m CMOS technology.

Shallow-trench isolation with raised-field-oxide structure

This paper describes a novel shallow-trench isolation (STI) structure to suppress the corner metal-oxide semiconductor field-effect transistor (MOSFET) inherent to trench isolation. A gate oxide and a thin polysilicon layer are first processed, and are then followed by the STI process. With this raised-field-oxide structure, the anomalous subthreshold conduction of the shallow-trench isolated MOSFETs due to electric-field crowding at the active edge has been successfully eliminated. No inverse-narrow-width effect is observed as the device width has been scaled down to 0.3 µm. The raised-field-oxide structure provides a larger process margin for planarization, and good device characteristics were achieved by this novel STI structure.

New Contact Etch Process for Embedded DRAM Applications

For embedded DRAM (E-DRAM) devices with feature sizes of 0.25 µm and beyond, contact processes with low contact resistance and low junction leakage current are required. The contact etch process needs to etch through multi-layer structures with SiO 2 , SiON/SiN layers and stop on Ti-polycide gate and Ti-salicide active regions at the same time. The key issues include high selectivity to TiSi x , vertical profile, complete removal of SiON/SiN cap layer and no polymer residues. In this paper, multi-layer contact etching without attacking TiSi x is reported. Using new process chemistry, the new contact etch process has been demonstrated for the manufacturing of 0.25 µm E-DRAM and beyond.

Low temperature processed poly-Si thin-film transistors with thinner LPD-SiO/sub 2/ as gate insulator and its reliability

The 10 nm-thick LPD-SiO/sub 2/ has been developed and applied as gate oxide to the low-temperature processed poly-Si TFTs with small geometry. The TFTs have large driving current, small threshold voltage, and small subthreshold swing. The reliability of the devices are also studied.