Jiangyi Li

Ultra-Compact and Robust Physically Unclonable Function Based on Voltage-Compensated Proportional-to-Absolute-Temperature Voltage Generators

This paper presents a technique for designing an ultra-compact and robust physically unclonable function for security-oriented applications. The circuits are based on pairs of analog circuits whose output voltage is supply voltage compensated and proportional to absolute temperature (PTAT). The difference between two outputs of a PTAT pair is digitized to produce 1 b output which is sensitive mostly only to random transistor threshold voltage variations. Fabricated in a 65 nm, the proposed 256 b PUF array takes an area of 3.07 μm2/bit, consumes 0.548 pJ/bit at a throughput of 10 Mb/s, while showing desirable robustness against temperature and supply voltage variations with 3.5% and 1.004% bit-instability across 0 to 80°C and 0.6 to 1.2 V, respectively. The unpredictability and uniqueness of the 256 b PUF output are verified by NIST randomness test and Hamming Distance between keys. As compared with the state of the art, the proposed design has an 8.3× smaller area/bit or 2× better robustness against noise and environmental variations.

Robust and In-Situ Self-Testing Technique for Monitoring Device Aging Effects in Pipeline Circuits

Runtime monitoring of aging effects in pipeline circuits is the key to dynamic reliability management techniques which can maximize the performance and energy-efficiency under a reliability envelope without imposing worst-case margin. The existing monitoring techniques are, however, severely limited: for sensor-based techniques, monitoring accuracy is significantly compromised due to the mismatches in aging conditions between sensors and the target circuits, as well as random variation of aging effects; for in-situ techniques, measurement results are sensitive to environmental variations during test phases, also severely reducing monitoring accuracy. We propose a new technique that enables accurate in-situ aging monitoring even under large environmental variations by (i) scaling the supply voltage for temperature-insensitive delay and (ii) reconfiguring target paths into ring oscillators, whose oscillation periods are measured and compared to pre-aging measurement to estimate aging-induced delay degradations. With additional accuracy-improving strategies, the technique achieves highly-accurate monitoring with an error of 15.5% across the temperature variations in self-test phases from 0°C to 80°C, exhibiting >30× improvement in accuracy as compared to the conventional technique operating at nominal supply voltage.

Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability

We present a triple-mode energy-harvesting power management unit (PMU) that interfaces a photovoltaic (PV) cell and delivers a regulated supply (VLoad) of 0.45V while storing remaining energy in a 3V rechargeable battery. The objective is to maximize the end-to-end conversion efficiency of the PMU against the variabilities of harvested energy and load power dissipation. Specifically, it uses an intermediate energy-storage capacitor to minimize the involvement (charging or discharging) of a battery in the conversion process over time. The experiments show that the proposed PMU can achieve 2.2× higher end-to-end conversion efficiency than the conventional dual-mode architectures when faced with typical variabilities in harvested energy and load power dissipation.

Energy-optimal voltage model supporting a wide range of nodal switching rates for early design-space exploration

This paper explores the models of the energy-optimal voltage (VOPT) of near/sub-threshold digital VLSI circuits with a focus on the support for a wide range of nodal switching rates. The previous models can estimate the VOPT of the circuits having relatively high nodal switching rates (VOPT, H), but can become inaccurate in finding the VOPT of the circuits having low nodal switching rate. In this work, therefore, we develop the models for finding (i) the VOPT of the circuits having low nodal switching rates (VOPT, L) and (ii) the critical nodal switching rate point (αcrit) below which the VOPT, L should be used. The models are verified with inverter chains and sub-threshold 10-transistor SRAM arrays in SPICE-level simulation. The model takes only process technology parameters to estimate VOPTs, and can be suitable for early-stage design-space exploration.

A technique to transform 6T-SRAM arrays into robust analog PUF with minimal overhead

Physically unclonable function (PUF) is one of the critical security primitives for key generation and storage. The key challenge in building a PUF is to achieve high robustness against noise, temperature/supply voltage (VDD) variations and device aging with low cost. This paper presents a technique to transform a pre-existing SRAM array into an analog PUF by configuring the access transistors in a 6T-SRAM bitcell into a pair of threshold voltage (Vth) sensors and comparing their outputs. The proposed analog PUF circuit achieves significantly better robustness than conventional SRAM-based PUFs using reset states while maintaining the benefit of hardware reuse: low area overhead. Test chips are prototyped in a 65nm CMOS to verify the randomness, uniqueness, and robustness of the proposed design.

An area-efficient microcontroller with an instruction-cache transformable to an ambient temperature sensor and a physically unclonable function

This paper presents a novel microcontroller-system-on-chip (μC-SοC) for pervasive sensing systems, with a 6T SRAM instruction cache dynamically transformable to an ambient temperature sensor and physically unclonable function (PUF). As those sensing and PUF operations are performed in a duty-cycled manner in targeted systems, the proposed transformation can save silicon area, e.g., by ∼9.8X as compared to dedicated sensor and PUF circuits that achieve comparable robustness with our temperature sensor and PUF. Specifically, the temperature sensor achieves −0.5/+1.5°C error with one-point calibration and 0.46°C/100mV power supply sensitivity; the PUF passes applicable NIST tests, achieves 0.97% unstable bits and 0.62% BER with TMV and comparator-input-swapping.

Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities

This paper presents a triple-mode, hybrid storage, energy-harvesting power management unit (EH PMU) that interfaces a photovoltaic cell, a regulated load, and a rechargeable battery. The objective is to maximize the end-to-end conversion efficiency of the EH PMU against temporal mismatch and variabilities of harvesting and load power. To minimize the involvement (charging or discharging) of a battery in the voltage conversion process, the proposed hybrid energy storage employs both battery and capacitor, which increases transient energy buffering capability and reduces the overall power conversion loss. Measurement results with 65-nm test chips show that the proposed EH PMU can achieve up to 2.2

A 3.07μm 2 /bitcell physically unclonable function with 3.5% and 1% bit-instability across 0 to 80°C and 0.6 to 1.2V in a 65nm CMOS

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Recent advances in in-situ and in-field aging monitoring and compensation for integrated circuits: Invited paper

higher end-to-end conversion efficiency than the conventional dual-mode architectures under testing cases emulating realistic load and harvesting power variabilities. We also devised a framework for the system design to guide capacitor sizing, buffering voltage range selection, and end-to-end efficiency tradeoffs.

An Area-Efficient Microprocessor-Based SoC With an Instruction-Cache Transformable to an Ambient Temperature Sensor and a Physically Unclonable Function

This paper presents a circuitry for physically unclonable function, generating a unique and stable key for security-oriented applications. The key is generated from an array of pairs of voltage-compensated proportional-to-absolute-temperature generators. The difference between two analog outputs of a pair is voltage- and temperature-compensated yet sensitive mostly only to random threshold-voltage variation. As compared to the state of the art [3-4], the proposed design has an 8.3× smaller bitcell or 3.66× higher robustness against noise and environmental variations.