Jianhua Li

A connectivity based clustering algorithm with application to VLSI circuit partitioning

Circuit partitioning is a fundamental problem in very large-scale integration (VLSI) physical design automation. In this brief, we present a new connectivity-based clustering algorithm for VLSI circuit partitioning. The proposed clustering method focuses on capturing natural clusters in a circuit, i.e., the groups of cells that are highly interconnected in a circuit. Therefore, the proposed clustering method can reduce the size of large-scale partitioning problems without losing partitioning solution qualities. The performance of the proposed clustering algorithm is evaluated on a standard set of partitioning benchmarks-ISPD98 benchmark suite. The experimental results show that by applying the proposed clustering algorithm, the previously reported best partitioning solutions from state-of-the-art partitioners are further improved.

Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement

The complexity and size of digital circuits have grown exponentially, and todays circuits can contain millions of logic elements. Clustering algorithms have become popular due to their ability to reduce circuit sizes, so that the circuit layout can be performed faster and with higher quality. This paper presents a deterministic net-reduction-based clustering algorithm called Net Cluster. The basic idea of the proposed technique is to put the emphasis on reducing the number of nets versus the number of cells, thereby capturing the natural clusters of a circuit. The proposed algorithm has proven a linear-time complexity of O(p), where p is the number of pins in a circuit. To demonstrate the effectiveness of the proposed clustering technique, it has been applied to multilevel partitioning and wire length-driven placement. The numerical experiments on the ISPD98 benchmark suite for partitioning and the ICCAD 2004 benchmark suite for placement demonstrate that by applying Net Cluster as a preprocessing step, the performance of state-of-the-art multilevel partitioners and placers can be further improved

Net cluster: a net-reduction based clustering preprocessing algorithm

The complexity and size of digital circuits have grown exponentially, and todays circuits can contain millions of logic elements. Clustering algorithms have become popular due to their ability to reduce circuit sizes, so that the circuit layout can be performed faster and with higher quality. This paper presents a deterministic net-reduction-based clustering algorithm called Net Cluster. The basic idea of the proposed technique is to put the emphasis on reducing the number of nets versus the number of cells, thereby capturing the natural clusters of a circuit. The proposed algorithm has proven a linear-time complexity of O(p), where p is the number of pins in a circuit. To demonstrate the effectiveness of the proposed clustering technique, it has been applied to multilevel partitioning and wire length-driven placement. The numerical experiments on the ISPD98 benchmark suite for partitioning and the ICCAD 2004 benchmark suite for placement demonstrate that by applying Net Cluster as a preprocessing step, the performance of state-of-the-art multilevel partitioners and placers can be further improved

A structure based clustering algorithm with applications to VLSI physical design

Clustering plays an important role in VLSI physical design. In this paper, we present a new structure and connectivity based clustering algorithm. The proposed clustering algorithm emphasizes capturing natural circuit clusters, i.e., highly interconnected cell groups. We apply the proposed clustering algorithm to 2-way and k-way partitionings on ISPD98 benchmark suite as stated in C. J. Alpert (1998), and 2-way partitioning to part of ISPD2005 benchmark suite based in G.-J. Nam et al. (2005). The experimental results show that the proposed clustering algorithm can maintain the partitioning solution qualities while reducing the sizes of large scale circuits.

Wirelength Based Clustering Technique for VLSI Physical Design

Physical design of Very Large Scale Integrated (VLSI) circuits is the phase where the physical shape of a circuit is decided. Layout is part of the physical design step where the locations of all circuit components and their wiring are decided. Layout typically consists of 3 stages: partitioning, placement, and routing. The main focus of this research is on the placement step. There are various efficient and effective academic placement tools. However, most of the placers ignore the global nets, long wires that span entire rows or columns of a circuit. Usually the global nets make up 10% of the total nets, but can comprise up to 50% of the total wirelength. In this work, a new clustering algorithm is designed to reduce the length of global nets. This new clustering algorithm clusters cells belonging to a global net if they have any other connections. The algorithm has been tested on ICCAD04 benchmark suite. The experimental results show that the total wirelength can be reduced for some test benchmarks by up to 8%.

A multilevel eigenvalue based circuit partitioning technique

VLSI circuit partitioning is an important step in the physical design of integrated circuits. In VLSI partitioning, a circuit is partitioned into smaller relatively independent sub-circuits. In this paper we present an eigenvalue based multilevel partitioning algorithm. The proposed method uses a matrix reordering technique to produce a minimal bandwidth matrix, relying upon matrix sparsity. The reordering technique is applied to the connectivity matrix of a clustered circuit and the matrix connectivity information is obtained. This connectivity information is used to partition the circuit. The experimental results demonstrate the techniques effectiveness against flat partitioning algorithms.

An effective congestion-based integer programming model for VLSI global routing

Global routing is a fundamental problem in VLSI physical design in which approximate paths for the interconnect (wires) of a circuit are decided. In this paper, a fast, order-free global routing technique is proposed by formulating the global routing problem as an integer linear programming (ILP) problem. A small set of high quality trees, in terms of congestion and length, for each net in the circuit is first produced. Then, a preprocessing technique is proposed to reduce problem sizes while maintaining solution quality. Evaluating performance on the IBM-place 2.0 suite shows a 19.5% average reduction in maximum channel capacity and a 71% average improvement in solving times compared to the traditional concurrent techniques. The proposed concurrent technique is also shown to be faster than the sequential router Labyrinth.

Clustering algorithms for circuit partitioning and placement problems

The complexity and size of digital circuits have grown exponentially, and todays circuits can contain millions of logic elements. Clustering algorithms have become popular due to their ability to reduce circuit sizes. Clustering enables circuit layout design problems, such as partitioning and placement to be performed faster and with higher quality. In this paper, current clustering algorithms and the effect of these algorithms on industry test benchmarks are studied. It is revealed that the score-based clustering algorithms are the most successful clustering techniques for circuit layout design and deserve more future research investigations.

A Structural Study and Hyperedge Clustering Technique for Large Scale Circuits

In this paper, a study of the effects of different clustering techniques on the structure of a circuit is performed with the intent of improving circuit partitioning results. In this study, each clustering technique is shown to have a signature effect on the majority of circuits in the ISPD98 benchmark suite. A score based hyperedge clustering technique is developed based on these results. The main focus of this technique is to first quickly find high quality clusters for a circuit while keeping the cells and net clustering ratios close to one another. The empirical results on ISPD98 benchmark circuits show that the application of the proposed technique can result in clustered circuits where the cell clustering ratio and the net clustering ratio are very close and runtime is improved and the partitioning solution is slightly enhanced