Jianjun Guo

A fast motion estimation algorithm based on diamond and triangle search patterns

Based on the directional characteristic of SAD (sum of absolute difference) distribution and the center-biased characteristic of motion vectors, a fast BMA (block-matching motion estimation algorithm), DLTS (diamond line/triangle search), is proposed in this paper. DLTS employs line search pattern (LP) or triangle search pattern (TP) adaptively according to the distance between the MBD (minimum block distortion) and SMBD (second MBD) points to locate the best matching block with large motion vector, and diamond search pattern(DP) to refine the motion vector. Although the proposed DLTS can also be trapped in local minima, the experimental results show that it is faster than DTS (diamond triangle search) and its encoding efficiency is almost the same as that of DTS.

Research on intra modes for inter-frame coding in H.264

It is well known that H.264 has great advantage of coding efficiency compared with the successful prior coding standards and it can save about 50% bit-rate under the same reconstructed picture quality. But the complexity of H.264 encoder is also very high. In order to improve the speed of the H.264 encoder, this paper researches the intra modes for inter-frame coding. The algorithm of mode decision for inter-frame coding is introduced and the complexity of the H.264 encoder is analyzed from the side of transform and quantization. In order to speed up the H.264 encoder without causing a great decrease in encoding efficiency, a fast intra mode decision method for inter-frame coding is also introduced. The experimental results show that the inter-frame coding with fast intra mode decision can reduce the computational complexity of the H.264 encoder remarkably while incurring little, if any, loss in quality.

A Fast Inter Mode Selection Algorithm for H.264

The high encoding efficiency of H.264 comes from many new video encoding technologies such as adopting variable block size in the process of motion estimation and compensation. But this increases the complexity of H.264 encoder greatly. The high encoding complexity limits the application of H.264 in the domain of real time video encoding. In order to decrease the complexity of H.264 encoder greatly, this paper proposes a fast inter mode selection algorithm to speed up the H.264 encoder. Experimental results show that the proposed algorithm can reduce the complexity of the inter mode decision remarkably while incurring little, if any, loss in quality

Analysis of inter-frame coding without intra modes in H.264/AVC

H.264/AVC is a new international standard for video coding which has great advantage of coding efficiency com-pared with other standards. It can save about 50% bit-rate compared with that of the successful prior coding stan-dards under the same reconstructed picture quality. But the high coding efficiency is acquired by heavily computa-tion. In this paper, the coding mode and algorithm for mode decision are introduced firstly, then transform and quantization are analyzed and experiments on inter-frame coding with or without intra modes are performed. The experiment results illustrate that the encoding method without intra modes in inter-frame coding will decrease the encoding time from 76.03% to 50.09% compared with that of the standard encoding method, while the PSNR-Y will change from -0.45dB to +0.20dB (most cases are ±0.10dB) at the same bit-rates.

A high performance heterogeneous architecture and its optimization design

The widely adoption of media processing applications provides great challenges to high performance embedded processor design. This paper studies a Data Parallel Coprocessor architecture based on SDTA and architecture de-cisions are made for the best performance/cost ratio. Experimental results on a prototype show that SDTA has high performance to run many embedded media processing applications. The simplicity and flexibility of SDTA encourages for further development for its reconfigurable functionality.

A heterogeneous multi-core processor architecture for high performance computing

The increasing application demands put great pressure on high performance processor design. This paper presents a multi-core System-on-Chip architecture for high performance computing. It is composed of a sparcv8-compliant LEON3 host processor and a data parallel coprocessor based on transport triggered architecture, all of which are tied with a 32-bit AMBA AHB bus. The LEON3 processor performs control tasks and the data parallel coprocessor performs computing intensive tasks. The chip is fabricated in 0.18um standard-cell technology, occupies about 5.3mm2 and runs at 266MHz.

Memory System Design for a Multi-core Processor

Multi-core processor has become hot research area recently. Cache results in high cost to maintain consistency between different data copies in multi-core processor especially in many-core processor. A hybrid memory architecture is proposed for the specific multi-core processor which uses cache for instruction while local storage for data. This paper focuses on the design and optimization of the proposed memory architecture. L1 instruction cache, local data storage, DMA engine, L2 cache and MMU is designed and optimized. L2 cache replacement strategy is studied to reduce the total miss cost.

Hierarchical memory system design for a heterogeneous multi-core processor

Multi-core architecture has become hot issue recently both for performance and power consideration. Memory system is the bottleneck under this circumstance. A multi-core architecture using simple cores based on transport triggered architecture is proposed. This architecture has a uniform programming view. The memory system design exploration and optimization is done and a hierarchical memory system is designed. A balanced memory bandwidth is provided to the multi-core architecture.

A fast motion estimation algorithm based on diamond and simplified square search patterns

Based on the directional characteristic of SAD(Sum of Absolute Difference) distribution and the center-biased characteristic of motion vectors, a fast BMA(block-matching motion estimation algorithm), DSSS(Diamond and Simplified Square Search), is proposed in this paper. DSSS employs line search pattern(LP), triangle search pattern(TP), or square pattern(SP) adaptively according to the distance between the MBD(Minimum Block Distortion) and SMBD(Second MBD) points to locate the best matching block with large motion vector, and diamond search pattern(DP) to refine the motion vector. Although the proposed DSSS may also be trapped in local minima, the experimental results show that it is faster than DS(Diamond Search) and DTS(Diamond and Triangle Search), while its encoding efficiency is better than DS and it is almost the same as that of DTS.

Research on fast block partition mode selection algorithm in H.264

The variable block size motion compensation using multiple reference frames is one of the key technologies to provide notable performance gain in H.264. However it is also the main bottleneck that increases the overall computational complexity. For this reason, based on some test results, this paper proposes a new biased fast mode decision method for H.264 video coding standard. Experimental results indicate that this method can speed up the H.264 encoder efficiently without noticeable loss in quality.