Wanghui Zou

Predictive calculation of coupling coefficient between on-chip small-area multilayer inductors

A predictive physics-based method for calculating the coupling coefficient between on-chip small-area multilayer inductors is proposed. The new method employs the symmetric approximation and is based on “ring-by-ring” manner, which provides a relatively easy way to estimate the crosstalk between on-chip inductors. The accuracy and effectiveness of the method is evaluated by comparing the calculated values with the electro-magnetic simulation results of a series of inductors with various design parameters. It has been verified that the calculation error of the new method is typically within around 4%.

An area-efficient 5GHz/10GHz dual-mode VCO with coupled helical inductors in 0.13-UM CMOS technology

The helical inductor is a three-dimensional multi-layer inductor with relatively higher quality factor and self-resonance frequency compare with other multi-layer inductors. A new dual-mode coupled-inductor VCO based on helical inductors is proposed, which is able to work on 5GHz and 10GHz band. Because of the helical inductors used, the proposed VCO is much more area-efficient than previous coupled-inductor structure. The simulation results show that the phase noise at 1 MHz offset is −101.6dBc/Hz and −101.3dBc/Hz at the frequency of 4.8GHz and 10.4GHz, respectively. The VCO draws 4mA from 1.2 V supply.

An analytical series resistance model for on-chip stacked inductors with inclusion of proximity effect between stacked layers

A predictive analytical series resistance model for stacked inductors is proposed, in which all model values are analytically calculated with geometric and process parameters. For stacked inductor, the series resistance is one of the most critical parameter, and is always strongly frequency dependent. The underlying mechanisms include the skin effect, the proximity effect between the inner and outer turns, and the proximity effect between the upper and the lower layers. In this letter, all of these effects are discussed and modeled accordingly, and the silicon measurement and simulation results are provided to show the accuracy of the proposed model.

A new high performance RF LDMOS with vertical n+n-p-p+ drain structure

An improved radio-frequency (RF) lateral double-diffused metal-oxide-semiconductor (LDMOS) device based on Si-substrate process is proposed. The structure is characterized by a p⁺-buried-layer (PBL) buried under the drain in the p-substrate region. A vertical n⁺n^-p^-p⁺ diode formed at the drain side helps deplete the n-drift region and lengthen the lateral drift distance, thus effectively increasing the device breakdown voltage (BV_DS) with negligible disturbances to the on-resistance (R_on) and RF performance as the PBL is far away from the carrier channel. Both theoretical analysis and simulations of PBL effects are demonstrated. Compared with the conventional device, the proposed RF-LDMOS device increase by 19.8% and 12.2% in BV_DS and BV_DS*f_t, respectively.

An improved analytical series resistance model for on-chip stacked inductors

An analytical series resistance model for on-chip stacked inductors with improved accuracy is proposed. As frequency increases and more metal layers are used, the proximity effect becomes very prominent for the series resistance. Through a precise modeling of the proximity effect in stacked inductors, the proposed model obtain a significant improvement on accuracy over the previous models. Numerical simulation and silicon measurement were performed to verify the model. The demonstrated supported the proposed model with an extended valid frequency range.

A 5.8-GHz Fully Integrated LNA with Solenoid Inductors in 0.18-µm CMOS Baseline Process

In this paper, we demonstrate the design of a 5.8-GHz fully integrated low noise amplifier (LNA) in 0.18-um CMOS technology. All devices, including passive and active devices, are realized in baseline process to reduce cost. To reduce area consumption of on-chip inductors and further reduce cost, the solenoid inductors are employed, therefore, the active area of the final layout is only 0.084 mm2. A 13.9 dB power gain and a 2.3 dB noise figure at 5.8-GHz are achieved with 9mW (1.8V, 5mA) power consumption. When the power consumption reduce to 3mW (1.5V, 2mA), the power gain and the noise figure become 11.9 dB and 2.5 dB, respectively.