Jianlong Chen

A Low-Power, High-Fidelity Stereo Audio Codec in 0.13

A 1.5 V low-power stereo audio codec in 0.13 μm CMOS is described. The microphone path includes a programmable gain stage with an enhanced transconductance cell followed by a continuous-time ΣΔ ADC with capacitive feed-forward and capacitive direct feedback. The speaker path employs a 1 mA Class-AB speaker amplifier with an improved quiescent current control circuit that delivers 30 mW to a 32 Ω speaker. The audio input and output paths achieve 92 and 98 dB dynamic range, respectively, with 6.5 mA total quiescent current.

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Circuit techniques that overcome practical noise, reliability, and EMI limitations are reported. An auxiliary loop with ramping circuits suppresses pop-and-click noise to 1 mV for an amplifier with 4 V-achievable output voltage. Switching edge rate control enables the system to meet the EN55022 Class-B standard with a 15 dB margin. An enhanced scheme detects short-circuit conditions without relying on overlimit current events.

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Mobile and portable devices like smartphones and tablets require headphone drivers that consume the lowest possible levels of quiescent current while operating directly from available battery voltages. Key headphone performance parameters for these devices are high dynamic range, high output power and low pop-and-click noise. This paper demonstrates a class-G headphone driver with 600μA/channel quiescent current that operates over a 2.95 to 4.5V supply range, which is compatible with Li-Ion batteries. This headphone driver achieves 108dB dynamic range, 62mW output power and 50μV pop-and-click noise.

Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers

A 40 nm CMOS analog front end (AFE) supporting HSPA/EDGE multimedia and enhanced audio applications is reported. The AFE consists of hi-fi audio and high-performance peripheral and auxiliary subsystems. Circuit techniques that enable a 200 μA audio RX path and a Class-AB driver with -80 dB THD are discussed. Audio playback and capture paths achieve 105 dB and 85 dB SNR, respectively.

A 62mW stereo class-G headphone driver with 108dB dynamic range and 600µA/channel quiescent current

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies 1 mm2 area while consuming 300 mW. The LNA consumes 130 mW and occupies 3 mm2 area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum.

A 40 nm CMOS analog front end with enhanced audio for HSPA/EDGE multimedia applications

Circuit techniques to overcome practical noise, reliability, and EMI limitations are reported. An auxiliary loop with ramping circuits suppresses pop-and-click noise to 1 mV for an amplifier with 4V achievable output voltage. Switching edge rate control enables the system to meet the EN55022 Class-B standard with a 15 dB margin. An enhanced scheme detects short-circuit conditions without relying on over-limit current events.

A 2.7 mW/Channel 48–1000 MHz Direct Sampling Full-Band Cable Receiver

Low-power and full-featured stereo audio CODECs are increasingly needed in wireless devices, such as Bluetooth headsets and smart phones. These portable devices are usually powered by low-voltage batteries with limited capacities. It is of particular importance that such CODECs be optimized for low-voltage operation and low-power consumption. The paper presents a 1.5V 10mW full-featured stereo audio CODEC that is integrated with a Bluetooth radio and PMU on a single die. As depicted in Fig. 4.5.1, the CODEC contains microphone PGAs, audio ΔΣ ADCs and DACs, speaker drivers and microphone bias generators.

Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices

We present a direct sampling full-band capture receiver for cable and digital TV applications. It consists of a 28nm CMOS ADC-based direct sampling receiver and a 0.18um BiCMOS LNA. It is capable of receiving 158 channels from 48MHz to 1000MHz simultaneously, achieving up to 10Gb/s data throughput, while exceeding DOCSIS requirements. The CMOS receiver occupies 1mm2 area while consuming 300mW. The LNA consumes 130mW. The total power dissipation from the receiver is 2.7mW per 6MHz channel.