Xicheng Jiang

A Low-Power, High-Fidelity Stereo Audio Codec in 0.13

A 1.5 V low-power stereo audio codec in 0.13 μm CMOS is described. The microphone path includes a programmable gain stage with an enhanced transconductance cell followed by a continuous-time ΣΔ ADC with capacitive feed-forward and capacitive direct feedback. The speaker path employs a 1 mA Class-AB speaker amplifier with an improved quiescent current control circuit that delivers 30 mW to a 32 Ω speaker. The audio input and output paths achieve 92 and 98 dB dynamic range, respectively, with 6.5 mA total quiescent current.

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A quad multi-speed (1.25/1.5625/2.5/3.125Gb/s) serializer/deserializer implemented in 0.25/spl mu/m CMOS technology is described. It uses a 4/spl times/ interleaved sample-and-hold receiver architecture. An analog adaptive receiver equalizer and a linear phase detector are used for clock and data recovery. At 3.125Gb/s, the serializer RMS jitter is 2.4ps. The serializer/deserializer runs error free for 2/sup 31/-1 PRBS data pattern over various length, up to 40-inches, of FR4 PCB trace.

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An integrated ultralow EMI Class-D amplifier with a feed-forward ADC and feedback filters is demonstrated in a 180 nm CMOS and wire-bonded package. Circuit and architecture techniques, which enable 1.75 W into an 8 Ohm speaker, 105 dB SNR, 95% efficiency, 0.004% THD+N, and 15.4 dB margin beyond the EN55022 Class-B standard, are discussed.

A quad multi-speed serializer/deserializer with analog adaptive equalization

Circuit techniques that overcome practical noise, reliability, and EMI limitations are reported. An auxiliary loop with ramping circuits suppresses pop-and-click noise to 1 mV for an amplifier with 4 V-achievable output voltage. Switching edge rate control enables the system to meet the EN55022 Class-B standard with a 15 dB margin. An enhanced scheme detects short-circuit conditions without relying on overlimit current events.

Integrated Class-D Audio Amplifier With 95% Efficiency and 105 dB SNR

An 82 mW fully integrated stereo ground-referenced headphone module is designed in 40 nm CMOS. Lower platform cost is enabled by integrating the headphone module on the same SoC as the baseband functions. Maintaining device reliability with direct battery hook-up and providing large output swing are major challenges for this work, and several techniques were employed to guarantee safe operation for all of the devices under various conditions. Area reduction techniques were utilized to reduce the die cost and achieve lower platform cost. The module supports direct battery hookup with a battery range from 3.1 to 4.5 V and achieves a minimum low frequency, i.e., 217 Hz, PSRR of 110 dB at the lowest battery voltage. Audio quality is preserved by achieving a dynamic range of 100 dB, THD+N of -84 dB at 10 mW output power, and 160 μV pop-and-click noise level during power-up and power-down. The module occupies an area of 0.675 mm 2 on the SoC.

Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers

A 40 nm CMOS analog front end (AFE) supporting HSPA/EDGE multimedia and enhanced audio applications is reported. The AFE consists of hi-fi audio and high-performance peripheral and auxiliary subsystems. Circuit techniques that enable a 200 μA audio RX path and a Class-AB driver with -80 dB THD are discussed. Audio playback and capture paths achieve 105 dB and 85 dB SNR, respectively.

A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies 1 mm2 area while consuming 300 mW. The LNA consumes 130 mW and occupies 3 mm2 area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum.

A 40 nm CMOS analog front end with enhanced audio for HSPA/EDGE multimedia applications

An integrated ultralow EMI Class-D amplifier with a feed-forward ADC and feedback filters is demonstrated in a 180 nm CMOS and wire-bonded package. Circuit and architecture techniques, which enables 1.75W into an 8 Ohm speaker, 105 dB dynamic range, 95% efficiency, 0.004% THD+N, and 15.4 dB margin beyond the EN55022 Class B standard, are discussed.

A 2.7 mW/Channel 48–1000 MHz Direct Sampling Full-Band Cable Receiver

Circuit techniques to overcome practical noise, reliability, and EMI limitations are reported. An auxiliary loop with ramping circuits suppresses pop-and-click noise to 1 mV for an amplifier with 4V achievable output voltage. Switching edge rate control enables the system to meet the EN55022 Class-B standard with a 15 dB margin. An enhanced scheme detects short-circuit conditions without relying on over-limit current events.

An 8Ω, 1.75W, 95% efficiency, 0.004% THD+N Class-D amplifier with a feed-forward ADC and feedback filters

A configurable three-level sigma-delta ADC for both DC measurement and audio conversion is implemented in a 40 nm CMOS process. It employs a switch-capacitor level shifter to increase the DC input range. Dynamic Element Matching (DEM), typically used in traditional multilevel feedback DAC, is avoided by setting proper common-mode (CM) voltage. Using a time-sharing technique, the three-level quantizer uses only one set of summer/comparator to save power and area. A simple analytical formula that accurately predicts DC measurement incremental noise is proposed to avoid overdesign. The ADC achieves 83 dB SNR and 79 dB peak SNDR for a 1 kHz audio input, and 11-bit accuracy for DC measurements with 100 kHz conversion rate, at the power of 0.5 mW.