Jinmei Lai

A novel memristor-based rSRAM structure for multiple-bit upsets immunity

A radiation hardened resistive SRAM structure (rSRAM) is proposed for the SRAM-based FPGAs in this paper. The rSRAM extends the conventional 6T SRAM structure by connecting memristors between the information nodes and drains of the transistors which compose cross-coupled invertors. With memristors connected to drains of OFF transistors configured to high resistance state while others configured to low resistance state forming stable voltage dividing path, the rSRAM structure is immune to both multiple-node upsets and multiplebit upsets (MBUs). The simulation result demonstrates that rSRAM cell can tolerate simultaneous disruptions affecting all sensitive nodes with an LET (Liner Energy Transfer) of 100Mev-cm2/mg.

A new FPGA packing algorithm based on the modeling method for logic block

Logic block packing is a necessary procedure of synthesis in FPGA CAD flow. In academic field, the existent packing algorithm, such as TV-Pack, is architecture-dependent and only applied to a certain type of logic blocks. In this paper, a novel function level modeling method for logic block is proposed. Furthermore, universal pack, a universal logic block packing algorithm based on this modeling, is presented and implemented. The experimental results show that this algorithm is architecture-independent and able to deal well with different types of logic blocks. Then the modeling method is proved to be right and quite effective for logic block packing

A New FPGA placement algorithm for heterogeneous resources

In this paper, we present a new placement algorithm targeted on a modern FPGA with heterogeneous logic and routing resources. This algorithm divides the heterogeneous resources of an FPGA into different logic layers, obtains a good initial placement by a quadratic method, and then employs low-temperature simulated annealing on each logic layer to determine the final location for all modules. Experiment result shows that the algorithm not only gains a saving of runtime by 27% compared with the classical approach of Versatile Place and Route (VPR) while having the same performance, but is also highly adaptable to modern FPGAs which have heterogeneous logic and routing resources1.

An FPGA configuration circuit used for fast and partial configuration

An improved architecture used for FPGAs fast and partial configuration is proposed. It is designed based on a 32 bits wide data bus, which can be controlled by a set of instructions. A partial control register and an address decoding logic are added in this design. Multiple configuration interfaces could be connected in this architecture, making hardware updating fast and convenient. Comparing with Virtex Series FPGAs configuration architecture, produced by Xilinx Corp., which only can configure memory cells by frame, this new architecture could configure any single memory cell in FPGA, offering more flexible configuration operations.

A novel net-partition-based multithread FPGA routing method

A platform-independent multithread routing method for FPGAs is proposed in this paper. Specifically, the proposed method includes two aspects for maximal parallelization. First, for high fanout net which usually takes considerable time to be routed due to large bounding boxes and number of terminals, it is partitioned into several subnets to be routed in parallel. Second, low fanout nets with non-overlapping bounding boxes are identified and routed in parallel as well to further speed up the routing process. A bounding box graph was constructed to facilitate the process of selecting nets to be routed concurrently. In addition, load balancing and synchronization strategies are introduced to raise routing efficiency and ensure the deterministic results. Experiments on different platforms and benchmarks with various combinations of high and low fanout nets are carried out. This technique improves the run-time by ~1.9 × with routing quality degrading by no more than 2.3%, on a quad-core processor platform.

Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions

An efficient minimisation method is presented to find the best polarity of fixed polarity canonical or-coincidence (COC) expansions. The method derives one COC fixed polarity expansion from another adjacent polarity expansion. To reduce CPU time, it utilises bitwise operation and Gray code. Furthermore, it counts the number of “0”s in the polarity matrix rather than polarity matrix multiplication. As a result, it makes minimisation for large functions within reasonable time practical. The space complexity of the proposed algorithm is O( M ) and time complexity is O(2 n ( M log M + M )) ( n and M are the number of input variables and the number of on-set COC maxterms).

Uniform routing architecture for FPGA with embedded IP cores

A uniform routing architecture is presented, which offers CLB, IOB and IP Cores an identical routing resource. At the same time, some method is adopted to optimize routing performance. With all unidirectional segmented lines and long lines with inserted tap buffers, this architecture is up to 9.8% faster compared with long lines without inserted buffers and on average 14.9% over bidirectional lines. Simulation results demonstrate our idea1.

Image filtering using partially and dynamically reconfiguration

Modular based partially and dynamically reconfigurable (PDR) FPGA system is an ideal solution for run-time image processing system which needs to change the function of the processing unit dynamically. Here we present a new PDR image filter based on our self-developed FDP FPGA Device. In this system, the transition bus (TB) structure is proposed for physical separation of the static/dynamic blocks as required in PDR system. And we demo the system with an image filter aimed at filtering out mix-noise. The experiment results show that the proposed PDR system meets the requirement of the run-time image filter by its flexibility, fast reconfiguration speed, and saving of logic resource.

PAM Map: An architecture-independent logic block mapping algorithm for SRAM-based FPGAs

In this paper, we consider the general problem of mapping a given logic circuit onto an SRAM-based FPGA with programmable logic blocks of arbitrary architectures. We formulate the problem as a graph matching problem and present an architecture-independent algorithm for this purpose. This algorithm also obtains a best area saving of 4% compared to architecture-dependent methods.

A 64/spl times/64-bit modified Booth multiplier utilizing multiplexer-select Booth encoder

In this paper, we describe a 64times64-bit high performance multiplier based on multiplexer cells which is implemented with pass transistor logic. A multiplexer-select Booth encoders was developed to increase speed and reduce the hardware cost. Moreover, a partitioned method was introduced in the design to save the propagate time of final adder. Realistic simulation using extracted timing parameters from the layout shows that the propagation time of the critical path is 2.82ns at 1.8V on 0.18mum CMOS technology