Jiayong Le

STAC: statistical timing analysis with correlation

Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter variations for sub-100nm technologies to produce an upper bound prediction on timing, it is equally important to consider the correlation of these variations for the bound to be useful. In this paper we present an efficient block-based statistical static timing analysis algorithm that can account for correlations from process parameters and re-converging paths. The algorithm can also accommodate dominant interconnect coupling effects to provide an accurate compilation of statistical timing information. The generality and efficiency for the proposed algorithm is obtained from a novel simplification technique that is derived from the statistical independence theories and principal component analysis (PCA) methods. The technique significantly reduces the cost for mean, variance and covariance computation of a set of correlated random variables.

Asymptotic probability extraction for non-normal distributions of circuit performance

While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear (e.g. quadratic) response surface models can be utilized to capture larger scale process variations; however, such models result in non-normal distributions for circuit performance which are difficult to capture since the distribution model is unknown. In this paper we propose an asymptotic probability extraction method, APEX, for estimating the unknown random distribution when using nonlinear response surface modeling. APEX first uses a binomial moment evaluation to efficiently compute the high order moments of the unknown distribution, and then applies moment matching to approximate the characteristic function of the random circuit performance by an efficient rational function. A simple statistical timing example and an analog circuit example demonstrate that APEX can provide better accuracy than Monte Carlo simulation with 10 samples and achieve orders of magnitude more efficiency. We also show the error incurred by the popular normal modeling assumption using standard IC technologies.

Asymptotic Probability Extraction for Nonnormal Performance Distributions

While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear response surface models (e.g., quadratic polynomials) can be utilized to capture larger scale process variations; however, such models result in nonnormal distributions for circuit performance. These performance distributions are difficult to capture efficiently since the distribution model is unknown. In this paper, an asymptotic-probability-extraction (APEX) method for estimating the unknown random distribution when using a nonlinear response surface modeling is proposed. The APEX begins by efficiently computing the high-order moments of the unknown distribution and then applies moment matching to approximate the characteristic function of the random distribution by an efficient rational function. It is proven that such a moment-matching approach is asymptotically convergent when applied to quadratic response surface models. In addition, a number of novel algorithms and methods, including binomial moment evaluation, PDF/CDF shifting, nonlinear companding and reverse evaluation, are proposed to improve the computation efficiency and/or approximation accuracy. Several circuit examples from both digital and analog applications demonstrate that APEX can provide better accuracy than a Monte Carlo simulation with 104 samples and achieve up to 10times more efficiency. The error, incurred by the popular normal modeling assumption for several circuit examples designed in standard IC technologies, is also shown

Projection-based performance modeling for inter/intra-die variations

Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such models requires significantly more simulation samples and solving much larger linear equations. In this paper, we propose a novel projection-based extraction approach, PROBE, to efficiently create quadratic response surface models and capture both inter-die and intra-die variations with affordable computation cost. PROBE applies a novel projection scheme to reduce the response surface modeling cost (i.e., both the required number of samples and the linear equation size) and make the modeling problem tractable even for large problem sizes. In addition, a new implicit power iteration algorithm is developed to find the optimal projection space and solve for the unknown model coefficients. Several circuit examples from both digital and analog circuit modeling applications demonstrate that PROBE can generate accurate response surface models while achieving up to 12/spl times/ speedup compared with the traditional methods.

Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions

In this paper we propose a novel projection-based algorithm to estimate the full-chip leakage power with consideration of both inter-die and intra-die process variations. Unlike many traditional approaches that rely on log-normal approximations, the proposed algorithm applies a novel projection method to extract a low-rank quadratic model of the logarithm of the full-chip leakage current and, therefore, is not limited to log-normal distributions. By exploring the underlying sparse structure of the problem, an efficient algorithm is developed to extract the non-log-normal leakage distribution with linear computational complexity in circuit size. In addition, an incremental analysis algorithm is proposed to quickly update the leakage distribution after changes to a circuit are made. Our numerical examples in a commercial 90nm CMOS process demonstrate that the proposed algorithm provides 4timeserror reduction compared with the previously proposed log-normal approximations, while achieving orders of magnitude more efficiency than a Monte Carlo analysis with 104 samples

Statistical performance modeling and optimization

As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing processes have introduced unavoidable and significant uncertainty in circuit performance; hence ensuring manufacturability has been identified as one of the top priorities of todays IC design problems. In this paper, we review various statistical methodologies that have been recently developed to model, analyze, and optimize performance variations at both transistor level and system level. The following topics will be discussed in detail: sources of process variations, variation characterization and modeling, Monte Carlo analysis, response surface modeling, statistical timing and leakage analysis, probability distribution extraction, parametric yield estimation and robust IC optimization. These techniques provide the necessary CAD infrastructure that facilitates the bold move from deterministic, corner-based IC design toward statistical and probabilistic design.

Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations

The large-scale process and environmental variations for todays nanoscale ICs require statistical approaches for timing analysis and optimization. In this paper, we demonstrate why the traditional concept of slack and critical path becomes ineffective under large-scale variations and propose a novel sensitivity framework to assess the ldquocriticalityrdquo of every path, arc, and node in a statistical timing graph. We theoretically prove that the path sensitivity is exactly equal to the probability that a path is critical and that the arc (or node) sensitivity is exactly equal to the probability that an arc (or a node) sits on the critical path. An efficient algorithm with incremental analysis capability is developed for fast sensitivity computation that has linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industrial examples.

A parametric approach for handling local variation effects in timing analysis

In this paper we propose a new methodology, called parametric on chip variation (POCV) analysis, to determine local process variation effects on the timing of designs. The proposed methodology requires relative delay and parasitic variations of cells and interconnects, respectively. Once this information is provided, delays and arrival times are propagated to calculate slacks as a function of these relative variations. A key characteristic of the POCV analysis is that it does not require a statistical library characterization or statistical RC extraction. The POCV method has been implemented in a timing analysis software, and tested on multiple production designs on 65 nm and 45 nm technology nodes, including multi-million instance designs. Our observation was that compared to the existing methods, POCV removes unrealistical pessimism on the setup paths and captures risks on the hold paths, with no changes to the existing timing sign-off environment.

Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics

As research begins to explore potential nanotechnologiesfor future post-CMOS integrated systems, modeling andsimulation environments must be developed that canaccommodate the corresponding problem complexity and non-traditionaldevice characteristics. This paper describes a circuit-levelsimulator that can accommodate an important class ofnanotechnology devices that are characterized by non-monotonicI-V characteristics. Employing adaptively controlledexplicit integration method (ACES) and piecewise linear (PWL)device models, the proposed approach effectively overcomesthe convergence problems and multiple equilibrium pointsolution problems caused by the Negative DifferentialResistance (NDR) regions in such device I-V functions.Importantly, the ACES approach can address the circuit sizeproblem when partitioning is included, and providecompatibility with simple I-V device model tables, therebyavoiding the need for analytical device models that rarely areavailable for nanotechnology devices.

Parametric analysis to determine accurate interconnect extraction corners for design performance

In this paper we propose a technique to determine accurate interconnect extraction corners for a 65-nm design using parametric RC extraction and timing analysis. We calculate the sensitivity of a design metric such as hold slack to each interconnect variation parameter. These sensitivities are then sorted for a selected number of critical paths. Finally, we utilize this information to determine the parameters which lead to extraction corner cases in the design. The results has shown that parametric analysis is necessary for a better interconnect variation coverage in the design.